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Multilevel logic synthesis
 Proc. IEEE
"... A survey of logic synthesis techniques for multilevel combinational logic is presented. The goal is to provide more indepth background and perspective for people interested in pursuing or assessing some of the topics in this emerging field. Introductions, capsule summaries, and, in some cases, deta ..."
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Cited by 118 (20 self)
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A survey of logic synthesis techniques for multilevel combinational logic is presented. The goal is to provide more indepth background and perspective for people interested in pursuing or assessing some of the topics in this emerging field. Introductions, capsule summaries, and, in some cases, detailed analysis, of the synthesis methods which have become established as practically significant are provided. Also included are some methods which
A Continuous Approach to Inductive Inference
 Mathematical Programming
, 1992
"... In this paper we describe an interior point mathematical programming approach to inductive inference. We list several versions of this problem and study in detail the formulation based on hidden Boolean logic. We consider the problem of identifying a hidden Boolean function F : f0; 1g n ! f0; 1g ..."
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Cited by 38 (2 self)
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In this paper we describe an interior point mathematical programming approach to inductive inference. We list several versions of this problem and study in detail the formulation based on hidden Boolean logic. We consider the problem of identifying a hidden Boolean function F : f0; 1g n ! f0; 1g using outputs obtained by applying a limited number of random inputs to the hidden function. Given this inputoutput sample, we give a method to synthesize a Boolean function that describes the sample. We pose the Boolean Function Synthesis Problem as a particular type of Satisfiability Problem. The Satisfiability Problem is translated into an integer programming feasibility problem, that is solved with an interior point algorithm for integer programming. A similar integer programming implementation has been used in a previous study to solve randomly generated instances of the Satisfiability Problem. In this paper we introduce a new variant of this algorithm, where the Riemannian metric used...
Multiple Boolean Relations
 in Workshop Notes of the Intl. Workshop on Logic Synthesis, (Tahoe City, CA
, 1993
"... Flexibility in selecting the Boolean functions to implement a digital circuit has various forms which have been studied in the literature such as don't care conditions, Boolean relations, and synchronous recurrence equations. Each of these represents a particular degree of flexibility that may be gi ..."
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Cited by 5 (3 self)
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Flexibility in selecting the Boolean functions to implement a digital circuit has various forms which have been studied in the literature such as don't care conditions, Boolean relations, and synchronous recurrence equations. Each of these represents a particular degree of flexibility that may be given in the description, inherent in the current representation, or derived from the surrounding environment. This flexibility is used to find an optimal implementation. In this paper, we propose a Multiple Boolean Relation (MBR) as a model that encompasses all degrees of freedom in choosing a set of Boolean functions to implement. This formulation unifies some of the recent work in logic synthesis, which has introduced new types of flexibility. We give examples of synthesis problems in which Multiple Boolean Relations arise and are the only model that represents all the flexibility available. We offer algorithms for obtaining an optimal solution to an MBR. 1 Introduction Optimization of Boo...
Optimization of MultiValued MultiLevel Networks
, 2002
"... A program called MVSIS has been developed which optimizes multilevel multivalued networks (MV networks). We describe what such a network is and the capabilities contained in MVSIS. MVSIS is modeled after SIS, which synthesizes binary multilevel networks, but the logic network of MVSIS is such tha ..."
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Cited by 3 (2 self)
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A program called MVSIS has been developed which optimizes multilevel multivalued networks (MV networks). We describe what such a network is and the capabilities contained in MVSIS. MVSIS is modeled after SIS, which synthesizes binary multilevel networks, but the logic network of MVSIS is such that all variables can be multivalued each with its own range. Included in MVSIS are almost all the technologyindependent transformations of SIS for combinational and sequential logic synthesis as well as transformations specific to multivalued nodes such as merge, pair decode, encode. MVSIS can read and write BLIFMV and BLIF files which describe MVnetworks and binary networks respectively.
Efficient reachability checking using sequential SAT
 in Proc. Asia South Pacific Design Automation Conf
, 2004
"... Abstract – Reachability checking and Preimage computation are fundamental problems in ATPG and formal verification. Traditional sequential search techniques based on ATPG/SAT, or on OBDDS have diverging strengths and weaknesses. In this paper, we describe how structural analysis and conflictbased ..."
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Cited by 2 (1 self)
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Abstract – Reachability checking and Preimage computation are fundamental problems in ATPG and formal verification. Traditional sequential search techniques based on ATPG/SAT, or on OBDDS have diverging strengths and weaknesses. In this paper, we describe how structural analysis and conflictbased learning are combined in order to improve the efficiency of sequential search. We use conflictbased learning and illegal state learning across timeframes. We also address issues in efficiently bounding the search space in a single timeframe and across timeframes. We analyze each of these techniques experimentally and demonstrate the advantages of each technique. We compare performance against a commercial sequential ATPG engine and VIS [13] on a set of standard benchmarks. I.
New Approach To Learning Noisy Boolean Functions
 in: Proceedings ICCIMA’98—International Conference on Computational Intelligence and Multimedia Applications, Gippsland
, 1998
"... this paper we are focusing on the Constructive Induction system based on Functional Decomposition ..."
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Cited by 2 (0 self)
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this paper we are focusing on the Constructive Induction system based on Functional Decomposition
On Using Logic Synthesis for Supervised Classification Learning
 7th IEEE International Conference on Tools with Artificial Intelligence, IEEE
, 1995
"... Learning from data is the central theme of Knowledge Discovery in Databases (KDD) and the Machine Learning (ML) community. In order to handle large databases, certain assumptions are necessary to make the problem tractable. Without introducing explicit domain knowledge, a natural assumption is Occam ..."
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Cited by 2 (1 self)
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Learning from data is the central theme of Knowledge Discovery in Databases (KDD) and the Machine Learning (ML) community. In order to handle large databases, certain assumptions are necessary to make the problem tractable. Without introducing explicit domain knowledge, a natural assumption is Occam's Razor. However, the requirement to find solutions of low complexity is not limited to KDD and ML. For example, in the logic synthesis community, low complexity solutions are sought for realizing circuits. Although the logic synthesis paradigms discussed here are certainly not new, it is still a relatively unknown phenomenon when referring to these tools' ability as machine learning programs. The purpose of this paper is to demonstrate the applicability of circuit design tools to the KDD and ML communities. Specifically, we will exhibit results from C4.5 (a typical machine learning algorithm), Espresso (a 2level minimization circuit design tool), and Function Extrapolation by Recomposing ...
MultipleValuedInput TANT Networks
 Proc. ISMVL'94
"... The paper proposes mvTANTs, threelevel networks with multiplevalued inputs and binary outputs. These networks are a generalization of binary TANTs (Three level And Not networks with True Inputs). One of possible interpretations of mvTANT is a fourlevel binary network with input decoders which rea ..."
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Cited by 1 (0 self)
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The paper proposes mvTANTs, threelevel networks with multiplevalued inputs and binary outputs. These networks are a generalization of binary TANTs (Three level And Not networks with True Inputs). One of possible interpretations of mvTANT is a fourlevel binary network with input decoders which realize multiplevalued literals. Similarly to mvPLAs, mvTANTs have regular structures with predictable timing. Comparing to mvPLAs, however, they have at least 25 % less input wires to the thirdlevel (NAND) plane and not more outputs from the secondlevel (AND) plane than the mvPLA. Thus, in many cases they have less gates and connections, and are useful to minimize Boolean functions in cellular FPGAs and other regular structures. 1 Introduction Some Electronically Programmable Logic Devices [27] and Cellular Field Programmable Gate Arrays, especially those from Motorola, Plessey, or Pilkington, require new kinds of logic synthesis tools, since the classical approaches, as well as the FPGAs...
Laboratoire de Microélectronique Faculté de Sciences Appliquées
, 1993
"... Finite State Machines: their relationship and their impact on the implementation Minimisation d’Etats et Codage d’Etats des Machines à Etats Finis: leur rapport et leur impact sur l’implementation Promoteurs: M. Davio (in memoriam) ..."
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Finite State Machines: their relationship and their impact on the implementation Minimisation d’Etats et Codage d’Etats des Machines à Etats Finis: leur rapport et leur impact sur l’implementation Promoteurs: M. Davio (in memoriam)
Certifiedby..........................................................
, 2004
"... requirements for the degrees of ..."