Linear time-invariant (LTI) phase noise theories provide important qualitative design insights but are limited in their quantitative predictive power. Part of the difficulty is that device noise undergoes multiple frequency translations to become oscillator phase noise. A quantitative understanding of this process requires abandoning the principle of time invariance assumed in most older theories of phase noise. Fortunately, the noise-to-phase transfer function of oscillators is still linear, despite the existence of the nonlinearities necessary for amplitude stabilization. In addition to providing a quantitative reconciliation between theory and measurement, the time-varying phase-noise model presented in this tutorial identifies the importance of symmetry in suppressing the upconversion of 1 noise into close-in phase noise, and provides an explicit appreciation of cyclostationary effects and AM--PM conversion. These insights allow a reinterpretation of why the Colpitts oscillator exh...

We present a method for optimizing and automating component and transistor sizing for CMOS LC oscillators. We observe that the performance measures can be formulated as posynomial functions of the design variables. As a result, the LC oscillator design problems can be posed as a geometric program, a special type of optimization problem for which very efficient global optimization methods have recently been developed. The synthesis method is therefore fast, and determines the globally optimal design; in particular the final solution is completely independent of the starting point (which can even be infeasible), and infeasible specifications are unambiguously detected. We can rapidly compute globally optimal trade-off curves between competing objectives such as phase noise and power.

Abstract—This paper presents a new physical theory of oscillator phase noise. Built around the concept of phase diffusion, this work bridges the fundamental physics of noise and existing oscillator phase-noise theories. The virtual damping of an ensemble of oscillators is introduced as a measure of phase noise. The explanation of linewidth compression through virtual damping provides a unified view of resonators and oscillators. The direct correspondence between phase noise and the Einstein relation is demonstrated, which reveals the underlying physics of phase noise. The validity of the new approach is confirmed by consistent experimental agreement. Index Terms—Analog integrated circuits, LC oscillators, oscillators, phase noise, radio-frequency (RF) circuits, resonators, ring oscillators. I.

In this work we review the processes of phase noise and jitter in electronic oscillators and the relationship between the two. Frequency and time domain simulation techniques and results are presented through the study of performance enhancement for a CMOS LC oscillator. The studied enhancements significantly reduce flicker noise upconversion, while the results demonstrate good agreement between time and frequency domain design approaches. 1.

Abstract—A monolithic and self-referenced radio frequency (RF) LC clock generator that is compliant with USB 2.0 is demonstrated in a system-on-chip (SoC). This work presents the first successful approach to replacing an external crystal (XTAL), the crystal oscillator (XO) and the phase-locked loop for clock generation in an IC supporting USB 2.0 using a standard CMOS fabrication process. It is shown that the primary design challenges with the implemented approach involve maintaining high frequency accuracy and low jitter. Techniques for addressing both are shown. In particular, the presented architecture exploits the effects of frequency division and low far-from-carrier phase noise to achieve low jitter. From a 1.536 GHz temperature-compensated LC reference oscillator, coherent clock signals are derived at 96 MHz for the SoC logic and 12 MHz for an on-chip full-speed USB PHY. Though self-referenced, approximately 400 ppm total frequency accuracy is achieved over process variations, 10 % variation in the USB power supply voltage and temperature variation from 10 to C85 C. Measured period and cycle-to-cycle jitter are 6.78 ps �� � and 8.96 ps �� � , respectively. Fabricated in a 0.35 m CMOS technology, the clock generator occupies 0.22 mm P and draws 9.5 mA from a 3.3-V supply, which is derived from the 5-V USB power supply. Index Terms—Analog integrated circuits, clocks, CMOSFET oscillators, frequency synthesizers, jitter, oscillator noise, oscillator stability, oscillators, phase-locked loops, phase noise, timing jitter. I.

The design of two 2.4GHz CMOS LC balanced oscillators in a 0.25µm process for Bluetooth specifications is presented. These oscillators achieve low phase noise with low power consumption. At a frequency offset of 3MHz from the 2.4GHz carrier, the simulated phase noise is –132dBc/Hz for both the oscillators with a power dissipation of 5-11mW from a 2.5V power supply. A wide tuning range of 18 % is obtained by means of a PMOS varactor in conjunction with an array of switched capacitors. 1.

This wireless transponder recovers power and a reference clock from an incident RF signal and returns data on a 900MHz carrier. A multi-stage voltage multiplier/rectifier converts the received low power RF signal to a useful DC voltage and stores the energy on a storage capacitor. The injection locking technique facilitates power efficient generation of a low phase noise 900MHz internal clock from the received 450MHz signal by employing a fully integrated low power LC oscillator. A fully integrated pseudodifferential power amplifier operating in class AB regime is used as the output stage of the system. The system dissipates an average of 5µA in standby mode and 1.1mA during active operation.

Abstract — A fully integrated 10 GHz LC voltage controlled oscillator is presented. The VCO is implemented in 6 metal 0.18�m CMOS process. The VCO achieves a wide tuning range of 20.1 % (10.20 GHz to 12.48 GHz), and provides an output power of –3 dBm, while drawing 22.7mA from 2.2V power supply. The measured phase noise is –125.33 dBc/Hz at 1 MHz offset from the carrier at 10.3GHz. The VCO figure of merit is a record low –188 dBc/Hz. I.

A new quadrature VCO (QVCO) is proposed with the NMOS back-gate as a coupling transistors. The advantage of proposed QVCO is analyzed in terms of power consumption and phase noise. Additional design techniques are applied to improve the symmetry of the complimentary VCO and to suppress the tail current noise contribution. The very low power QVCO has been fabricated in 0.18um CMOS technology for 1GHz band operation and obtained phase noise of-120 dBc/Hz at 1MHz offset while dissipating only 3mA for the whole QVCO from 1.8V supply. I.

Underlying physical mechanisms controlling the noise properties of oscillators are studied. This treatment shows the importance of inductance selection for oscillator noise optimization. A design strategy centered around an inductance selection scheme is executed using a practical graphical optimization method to optimize phase noise subject to design constraints such as power dissipation, tank amplitude, tuning range, startup condition, and diameters of spiral inductors. The optimization technique is demonstrated through a design example, leading to a 2.4-GHz fully integrated, LC voltage-controlled oscillator (VCO) implemented using 0.35- m MOS transistors. The measured phase-noise values are 121, 117, and 115 dBc/Hz at 600-kHz offset from 1.91, 2.03, and 2.60-GHz carriers, respectively. The VCO dissipates 4 mA from a 2.5-V supply voltage. The inversion mode MOSCAP tuning is used to achieve 26% of tuning range. Two figures of merit for performance comparison of various oscillators are introduced and used to compare this work to previously reported results.