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57
Hajimiri A. Oscillator Phase Noise: a Tutorial
 IEEE Journal of SolidState Circuits
, 2000
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A NoiseShifting Differential Colpitts VCO
 IEEE Journal of Solid State Circuits
, 2002
"... Abstract—A novel noiseshifting differential Colpitts VCO is presented. It uses current switching to lower phase noise by cyclostationary noise alignment and improve the startup condition. A design strategy is also devised to enhance the phase noise performance of quadrature coupled oscillators. ..."
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Abstract—A novel noiseshifting differential Colpitts VCO is presented. It uses current switching to lower phase noise by cyclostationary noise alignment and improve the startup condition. A design strategy is also devised to enhance the phase noise performance of quadrature coupled oscillators. Two integrated VCOs are presented as design examples. Index Terms—Analog integrated circuits, CMOS integrated circuits, LC oscillators, optimization, phase noise, quadrature oscillators, radio frequency, voltagecontrolled oscillators. I.
Virtual damping and Einstein relation in oscillators
 IEEE Journal of Solid State Circuits
, 2003
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Design and optimization of LC oscillators
, 1999
"... We present a method for optimizing and automating component and transistor sizing for CMOS LC oscillators. We observe that the performance measures can be formulated as posynomial functions of the design variables. As a result, the LC oscillator design problems can be posed as a geometric program, ..."
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Cited by 8 (2 self)
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We present a method for optimizing and automating component and transistor sizing for CMOS LC oscillators. We observe that the performance measures can be formulated as posynomial functions of the design variables. As a result, the LC oscillator design problems can be posed as a geometric program, a special type of optimization problem for which very efficient global optimization methods have recently been developed. The synthesis method is therefore fast, and determines the globally optimal design; in particular the final solution is completely independent of the starting point (which can even be infeasible), and infeasible specifications are unambiguously detected. We can rapidly compute globally optimal tradeoff curves between competing objectives such as phase noise and power.
CMOS RF Integrated Circuits at 5 GHz and Beyond
 Proceedings of the IEEE
, 2000
"... A strong demand for wireless products, an insatiable thirst for spectrum that pushes carrier frequencies ever upward, and the constant quest for higher performance at lower power and cost, have recently driven the development of radio frequency integrated circuit (RF IC) technology in unprecedente ..."
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A strong demand for wireless products, an insatiable thirst for spectrum that pushes carrier frequencies ever upward, and the constant quest for higher performance at lower power and cost, have recently driven the development of radio frequency integrated circuit (RF IC) technology in unprecedented ways. These pressures are stimulating novel solutions that allow RF ICs to enjoy more of the benefits of Moore’s law than has been the case in the past. In addition to regular raw transistor speed increases, the growing number of interconnect layers allows the realization of improved inductors, capacitors, and transmission lines. A deeper understanding of noise at both the device and circuit level has improved the performance of low noise amplifiers (LNAs) and oscillators. Finally, an appropriate raiding of circuit ideas dating back to the vacuum tube era enables excellent performance, even when working close to the limits of a technology. This paper surveys some of these developments in the context of lowpower RF CMOS technology, with a focus on an illustrative implementation of a lowpower 5GHz wireless LAN receiver in 0.25m CMOS. Thanks to these recent advances in passive components and active circuits, the blocks comprising the receiver consume a total of approximately 37 mW. These blocks include an imagereject LNA, imagereject downconverter, and a complete frequency synthesizer. The overall noise figure is 5 dB, and the inputreferred thirdorder intercept (IIP3) is 2 dBm. To underscore that 5 GHz does not represent an upper bound by any means, this paper concludes with a look at active circuits that function beyond 15–20 GHz, and a characterization of onchip transmission lines up to 50 GHz, all in the context of how scaling is expected to shape future developments. Keywords—CMOS, HIPERLAN, LAN, radio, receiver, RF IC, transceiver, transmitter, wireless LAN.
Standing wave oscillators utilizing waveadaptive tapered transmission lines
 in IEEE Symp. VLSI Circuits Dig. Tech. Papers
, 2004
"... Abstract—In this paper, we introduce a novel standing wave oscillator (SWO) utilizing standingwaveadaptive tapered transmission lines. This structure enhances and lowers phase noise through lossreducing shaping of the transmission line, such that it is adapted to the positiondependent amplitude ..."
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Abstract—In this paper, we introduce a novel standing wave oscillator (SWO) utilizing standingwaveadaptive tapered transmission lines. This structure enhances and lowers phase noise through lossreducing shaping of the transmission line, such that it is adapted to the positiondependent amplitudes of standing waves. Measurements validate the advantages of the proposed technique. The phase noise of a MOS SWO with the tapered line is 5–10 dB less than that of a uniformline MOS SWO over a wide range of offset frequencies, centered about 15 GHz. Demonstrating a valuable exploitation of standing wave properties, the novel design concept boosts the potential for the emergence of standing wave oscillators as a useful alternative to the traditional lumped oscillator. Index Terms—Integrated circuits, oscillators, phase noise, quality factor, radiofrequency (RF), standing waves, standing wave oscillators, tapered transmission lines, transmission lines. I.
Study and simulation of CMOS LC oscillator phase noise and jitter
 Proceedings of the 2003 International Symposium on Circuit and Systems, Volume: 1, Pages:I665  I668
, 2003
"... In this work we review the processes of phase noise and jitter in electronic oscillators and the relationship between the two. Frequency and time domain simulation techniques and results are presented through the study of performance enhancement for a CMOS LC oscillator. The studied enhancements sig ..."
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In this work we review the processes of phase noise and jitter in electronic oscillators and the relationship between the two. Frequency and time domain simulation techniques and results are presented through the study of performance enhancement for a CMOS LC oscillator. The studied enhancements significantly reduce flicker noise upconversion, while the results demonstrate good agreement between time and frequency domain design approaches. 1.
A Monolithic and SelfReferenced RF LC Clock Generator Compliant With USB 2.0
"... Abstract—A monolithic and selfreferenced radio frequency (RF) LC clock generator that is compliant with USB 2.0 is demonstrated in a systemonchip (SoC). This work presents the first successful approach to replacing an external crystal (XTAL), the crystal oscillator (XO) and the phaselocked loop ..."
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Cited by 4 (4 self)
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Abstract—A monolithic and selfreferenced radio frequency (RF) LC clock generator that is compliant with USB 2.0 is demonstrated in a systemonchip (SoC). This work presents the first successful approach to replacing an external crystal (XTAL), the crystal oscillator (XO) and the phaselocked loop for clock generation in an IC supporting USB 2.0 using a standard CMOS fabrication process. It is shown that the primary design challenges with the implemented approach involve maintaining high frequency accuracy and low jitter. Techniques for addressing both are shown. In particular, the presented architecture exploits the effects of frequency division and low farfromcarrier phase noise to achieve low jitter. From a 1.536 GHz temperaturecompensated LC reference oscillator, coherent clock signals are derived at 96 MHz for the SoC logic and 12 MHz for an onchip fullspeed USB PHY. Though selfreferenced, approximately 400 ppm total frequency accuracy is achieved over process variations, 10 % variation in the USB power supply voltage and temperature variation from 10 to C85 C. Measured period and cycletocycle jitter are 6.78 ps �� � and 8.96 ps �� � , respectively. Fabricated in a 0.35 m CMOS technology, the clock generator occupies 0.22 mm P and draws 9.5 mA from a 3.3V supply, which is derived from the 5V USB power supply. Index Terms—Analog integrated circuits, clocks, CMOSFET oscillators, frequency synthesizers, jitter, oscillator noise, oscillator stability, oscillators, phaselocked loops, phase noise, timing jitter. I.
17.2 A CMOS Differential NoiseShifting Colpitts VCO
"... Demand for higher numbers of communication channels imposes tighter phase noise performance for the local oscillators. Crosscoupled oscillators are widely used due to ease of implementation and differential operation (Figure 17.2.1a) [1,2,3]. Unfortunately, in crosscoupled VCOs the maximum noise ..."
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Demand for higher numbers of communication channels imposes tighter phase noise performance for the local oscillators. Crosscoupled oscillators are widely used due to ease of implementation and differential operation (Figure 17.2.1a) [1,2,3]. Unfortunately, in crosscoupled VCOs the maximum noise generation instant coincides with maximum phase noise sensitivity and hence the crosscoupled VCOs do not use the full potential of the resonator [3]. This oscillator topology achieves improved phase noise for a given quality factor and bias current by alternating the bias current and aligning the maximum noise with the least sensitive time in the cycle. The phase noise of an oscillator is given by [4]: (1) where foff is the offset frequency from the carrier, qmax is the maximum signal charge swing, i2n /∆f is the power spectral density of
Minimum Phase Noise of an LC oscillator: Determination of the optimal operating point of the active part
, 2012
"... In this paper, we describe an original method for determining the optimal operating point of the active part (transistor) of an LC oscillator leading to the minimum phase noise for given specifications in terms of power consumption, oscillation frequency and for given devices (i.e., transistor and r ..."
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In this paper, we describe an original method for determining the optimal operating point of the active part (transistor) of an LC oscillator leading to the minimum phase noise for given specifications in terms of power consumption, oscillation frequency and for given devices (i.e., transistor and resonator). The key point of the proposed method is based on the use of a proper LC oscillator architecture providing a fixed loaded quality factor for different operating points of the active part within the oscillator. The feedback network of this architecture is made of an LC resonator with coupling transformers. In these conditions, we show that it is possible to easily change the operating point of the amplifier, through the determination of the turns ratio of those transformers, and observe its effect on phase noise without modifying the loaded quality factor of the resonator. The optimal operating point for minimum phase noise is then extracted from nonlinear simulations. Once this optimal behaviour of the active part known and by associating the previous LC resonator, a design of an LC oscillator or VCO with an optimal phase noise becomes possible. The conclusions of the presented simulation results have been widely used to design and implement a fully integrated, LC differential VCO on a 0.35 µm BiCMOS SiGe process.