Ordered Binary Decision Diagrams (OBDDs) have found widespread use in CAD applications such as formal verification, logic synthesis, and test generation. OBDDs represent Boolean functions in a form that is both canonical and compact for many practical cases. They can be generated and manipulated by efficient graph algorithms. Researchers have found that many tasks can be expressed as series of operations on Boolean functions, making them candidates for OBDD-based methods. The success of OBDDs has inspired efforts to improve their efficiency and to expand their range of applicability. Techniques have been discovered to make the representation more compact and to represent other classes of functions. This has led to improved performance on existing OBDD applications, as well as enabled new classes of problems to be solved. This paper provides an overview of the state of the art in graph-based function representations. We focus on several recent advances of particular importance for forma...

Binary Moment Diagrams (BMDs) provide a canonical representations for linear functions similar to the way Binary Decision Diagrams (BDDs) represent Boolean functions. Within the class of linear functions, we can embed arbitary functions from Boolean variables to real, rational, or integer values. BMDs can thus model the functionality of data path circuits operating over word level data. Many important functions, including integer multiplication, that cannot be represented efficiently at the bit level with BDDs have simple representations at the word level with BMDs. Furthermore, BMDs can represent Boolean functions with around the same complexity as BDDs. We propose

e�mail � emc�cs.cmu.edu e�mail � masahiro�eecs.berkeley.edu e�mail � xzhao�cs.cmu.edu Abstract � Functions that map boolean vectors into the in� tegers are important for the design and veri�cation of arith� metic circuits. MTBDDs and BMDs have been proposed for representing this class of functions. We discuss the relation� ship between these methods and describe a generalization called hybrid decision diagrams which is often much more concise. We show how to implement arithemetic operations e�ciently for hybrid decision diagrams. In practice � this is one of the main limitations of BMDs since performing arith� metic operations on functions expressed in this notation can be very expensive. In order to extend symbolic model check� ing algorithms to handle arithmetic properties � it is essential to be able to compute the BDD for the set of variable as� signments that satisfy an arithmetic relation. In our paper� we give an e�cient algorithm for this purpose. Moreover� we prove that for the class of linear expressions � the time complexity of our algorithm is linear in the number of vari� ables. 1

This paper presents a new data structure called Boolean Expression Diagrams (BEDs) for representing and manipulating Boolean functions. BEDs are a generalization of Binary Decision Diagrams (BDDs) which can represent any Boolean circuit in linear space and still maintain many of the desirable properties of BDDs. Two algorithms are described for transforming a BED into a reduced ordered BDD. One is a generalized version of the BDD apply-operator while the other can exploit the structural information of the Boolean expression. This ability is demonstrated by verifying that two di erent circuit implementations of a 16-bit multiplier implement the same Boolean function. Using BEDs, this veri cation problem is solved in less than a second, while using standard BDD techniques this problem is infeasible. Generally, BEDs are useful in applications, for example tautology checking, where the end-result as a reduced ordered BDD is small.

We prerent methods to minimize F&d Polarity Reed-hiuller ezpnrrionr (FPRMr), i.e. t-level jized polarity AND/RXOR canonical rcpnrcntatiow of Boolean func-tionr, uring Ordered l&actional De&ion Diagnamr (OF-DDE). We investigate the close relation between both np-nrentationr and uee eficient algorithmr on OFDDI for ez-act and heutirtic minimization of FPRMz. In contrtut to pnviov~rlg published methoda our algorithm can alro handle circuit8 with reveral outpuk. Ezpcrimental nrultr on large benchmarkr are given to rhow the eficiency of our ap-pmch. 1 Iutroduction The high complezity of modem VLSI circuitry has shown an increasing demand for synthesis tools. In the

Decision Diagrams (DDs) are used in many applications in CAD. Various types of DDs, e.g. BDDs, FDDs, KFDDs, differ by their decomposition types. In this paper we investigate the different decomposition types and prove that there are only three that really help to reduce the size of DDs. 1 Introduction Decision Diagrams (DDs) are successfully applied in many fields of design automation, e.g. [17, 4, 1, 14, 7, 24, 11, 2, 9]. The most popular type of DD is the Ordered Binary Decision Diagram (OBDD) allowing efficient representation and manipulation of Boolean functions [5]. The more recent techniques have made it possible to handle (some) large functions without any basic variation of the OBDD concept itself. The dynamic variable ordering with sifting introduced by Rudell [21] allows to represent examples which could not be represented by any previous heuristic methods. Moreover, the variable ordering in [21] is handled by the package itself, alleviating the need for variable ordering ...

We present a data structure for Boolean functions, which we call Parity--OBDDs or \Phi-- OBDDs, which combines the nice algorithmic properties of the well--known ordered binary decision diagrams (OBDDs) with a considerably larger descriptive power. Beginning from an algebraic characterization of the \Phi--OBDD complexity we prove in particular that the minimization of the number of nodes, the synthesis, and the equivalence test for \Phi--OBDDs, which are the fundamental operations for circuit verification, have efficient deterministic solutions. Several functions of pratical interest, i.e. the indirect storage access function, have exponential ODBB--size but are of polynomial size if \Phi--OBDDs are used. Keywords: data structures for Boolean functions, BDDs, circuit verification 1 Introduction Formal circuit verification is a fundamantal task. The following approach for verification is often used (for a survey see [8] and [21]). A data structure for representing Boolean functions is...

The combinational logic-level equivalence problem is to determine whether two given combinational circuits implement the same Boolean function. This problem arises in a number of CAD applications, for example when checking the correctness of incremental design changes (performed either manually or by a design automation tool). This paper introduces a data structure called Boolean Expression Diagrams (BEDs) and two algorithms for transforming a BED into a Reduced Ordered Binary Decision Diagram (OBDD). BEDs are capable of representing any Boolean circuit in linear space and can exploit structural similarities between the two circuits that are compared. These properties make BEDs suitable for verifying the equivalence of combinational circuits. BEDs can be seen as an intermediate representation between circuits (which are compact) and OBDDs (which are canonical). Based on a large number of combinational circuits, we demonstrate that BEDs either outperform or achieve results comparable to...

With the increasing complexity of protocol and circuit designs, formal verification has become an important research area and binary decision diagrams (BDDs) have been shown to be a powerful tool in formal verification. This paper presents a parallel algorithm for BDD construction targeted at shared memory multiprocessors and distributed shared memory systems. This algorithm focuses on improving memory access locality through specialized memory managers and partial breadth-first expansion, and on improving processor utilization through dynamic load balancing. The results on a shared memory system show speedups of over two on four processors and speedups of up to four on eight processors. The measured results clearly identify the main source of bottlenecks and point out some interesting directions for further improvements. 1 Introduction With the increasing complexity of protocol and circuit designs, formal verification has become an important research area. As an example, in 1994, In...

Data structures such as *BMDs, HDDs, and K*BMDs provide compact representations for functions which map Boolean vectors into integer values, but not floating point values. In this paper, we propose a new data structure, called Multiplicative Power Hybrid Decision Diagrams (*PHDDs), to provide a compact representation for functions that map Boolean vectors into integer or floating point values. The size of the graph to represent the IEEE floating point encoding is linear with the word size. The complexity of floating point multiplication grows linearly with the word size. The complexity of floating point addition grows exponentially with the size of the exponent part, but linearly with the size of the mantissa part. We applied *PHDDs to verify integer multipliers and floating point multipliers before the rounding stage, based on a hierarchical verification approach. For integer multipliers, our results are at least 6 times faster than *BMDs. Previous attempts at verifying floating point multipliers required manual intervention. We verified floating point multipliers before the rounding stage automatically.