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62
Binary Decision Diagrams and Beyond: Enabling Technologies for Formal Verification
, 1995
"... Ordered Binary Decision Diagrams (OBDDs) have found widespread use in CAD applications such as formal verification, logic synthesis, and test generation. OBDDs represent Boolean functions in a form that is both canonical and compact for many practical cases. They can be generated and manipulated by ..."
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Cited by 104 (0 self)
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Ordered Binary Decision Diagrams (OBDDs) have found widespread use in CAD applications such as formal verification, logic synthesis, and test generation. OBDDs represent Boolean functions in a form that is both canonical and compact for many practical cases. They can be generated and manipulated by efficient graph algorithms. Researchers have found that many tasks can be expressed as series of operations on Boolean functions, making them candidates for OBDDbased methods. The success of OBDDs has inspired efforts to improve their efficiency and to expand their range of applicability. Techniques have been discovered to make the representation more compact and to represent other classes of functions. This has led to improved performance on existing OBDD applications, as well as enabled new classes of problems to be solved. This paper provides an overview of the state of the art in graphbased function representations. We focus on several recent advances of particular importance for forma...
Verification of Arithmetic Functions with Binary Moment Diagrams
 IN DESIGN AUTOMATION CONF
, 1994
"... Binary Moment Diagrams (BMDs) provide a canonical representations for linear functions similar to the way Binary Decision Diagrams (BDDs) represent Boolean functions. Within the class of linear functions, we can embed arbitary functions from Boolean variables to real, rational, or integer values. BM ..."
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Cited by 97 (6 self)
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Binary Moment Diagrams (BMDs) provide a canonical representations for linear functions similar to the way Binary Decision Diagrams (BDDs) represent Boolean functions. Within the class of linear functions, we can embed arbitary functions from Boolean variables to real, rational, or integer values. BMDs can thus model the functionality of data path circuits operating over word level data. Many important functions, including integer multiplication, that cannot be represented efficiently at the bit level with BDDs have simple representations at the word level with BMDs. Furthermore, BMDs can represent Boolean functions with around the same complexity as BDDs. We propose
Hybrid decision diagrams  overcoming the limitations of MTBDDs and BMDs
 In Int'l Conf. on CAD
, 1995
"... e�mail � emc�cs.cmu.edu e�mail � masahiro�eecs.berkeley.edu e�mail � xzhao�cs.cmu.edu Abstract � Functions that map boolean vectors into the in� tegers are important for the design and veri�cation of arith� metic circuits. MTBDDs and BMDs have been proposed for representing this class of functions. ..."
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Cited by 55 (3 self)
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e�mail � emc�cs.cmu.edu e�mail � masahiro�eecs.berkeley.edu e�mail � xzhao�cs.cmu.edu Abstract � Functions that map boolean vectors into the in� tegers are important for the design and veri�cation of arith� metic circuits. MTBDDs and BMDs have been proposed for representing this class of functions. We discuss the relation� ship between these methods and describe a generalization called hybrid decision diagrams which is often much more concise. We show how to implement arithemetic operations e�ciently for hybrid decision diagrams. In practice � this is one of the main limitations of BMDs since performing arith� metic operations on functions expressed in this notation can be very expensive. In order to extend symbolic model check� ing algorithms to handle arithmetic properties � it is essential to be able to compute the BDD for the set of variable as� signments that satisfy an arithmetic relation. In our paper� we give an e�cient algorithm for this purpose. Moreover� we prove that for the class of linear expressions � the time complexity of our algorithm is linear in the number of vari� ables. 1
Boolean Expression Diagrams
, 1997
"... This paper presents a new data structure called Boolean Expression Diagrams (BEDs) for representing and manipulating Boolean functions. BEDs are a generalization of Binary Decision Diagrams (BDDs) which can represent any Boolean circuit in linear space and still maintain many of the desirable proper ..."
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Cited by 46 (5 self)
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This paper presents a new data structure called Boolean Expression Diagrams (BEDs) for representing and manipulating Boolean functions. BEDs are a generalization of Binary Decision Diagrams (BDDs) which can represent any Boolean circuit in linear space and still maintain many of the desirable properties of BDDs. Two algorithms are described for transforming a BED into a reduced ordered BDD. One is a generalized version of the BDD applyoperator while the other can exploit the structural information of the Boolean expression. This ability is demonstrated by verifying that two di erent circuit implementations of a 16bit multiplier implement the same Boolean function. Using BEDs, this veri cation problem is solved in less than a second, while using standard BDD techniques this problem is infeasible. Generally, BEDs are useful in applications, for example tautology checking, where the endresult as a reduced ordered BDD is small.
Fast ofdd based minimization of fixed polarity reedmuller expressions
 In European Design Automation Conf
, 1994
"... We prerent methods to minimize F&d Polarity Reedhiuller ezpnrrionr (FPRMr), i.e. tlevel jized polarity AND/RXOR canonical rcpnrcntatiow of Boolean functionr, uring Ordered l&actional De&ion Diagnamr (OFDDE). We investigate the close relation between both npnrentationr and uee eficient algorithm ..."
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Cited by 26 (16 self)
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We prerent methods to minimize F&d Polarity Reedhiuller ezpnrrionr (FPRMr), i.e. tlevel jized polarity AND/RXOR canonical rcpnrcntatiow of Boolean functionr, uring Ordered l&actional De&ion Diagnamr (OFDDE). We investigate the close relation between both npnrentationr and uee eficient algorithmr on OFDDI for ezact and heutirtic minimization of FPRMz. In contrtut to pnviov~rlg published methoda our algorithm can alro handle circuit8 with reveral outpuk. Ezpcrimental nrultr on large benchmarkr are given to rhow the eficiency of our appmch. 1 Iutroduction The high complezity of modem VLSI circuitry has shown an increasing demand for synthesis tools. In the
How many Decomposition Types do we need ?
 In European Design & Test Conf
, 1995
"... Decision Diagrams (DDs) are used in many applications in CAD. Various types of DDs, e.g. BDDs, FDDs, KFDDs, differ by their decomposition types. In this paper we investigate the different decomposition types and prove that there are only three that really help to reduce the size of DDs. 1 Introduct ..."
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Cited by 22 (6 self)
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Decision Diagrams (DDs) are used in many applications in CAD. Various types of DDs, e.g. BDDs, FDDs, KFDDs, differ by their decomposition types. In this paper we investigate the different decomposition types and prove that there are only three that really help to reduce the size of DDs. 1 Introduction Decision Diagrams (DDs) are successfully applied in many fields of design automation, e.g. [17, 4, 1, 14, 7, 24, 11, 2, 9]. The most popular type of DD is the Ordered Binary Decision Diagram (OBDD) allowing efficient representation and manipulation of Boolean functions [5]. The more recent techniques have made it possible to handle (some) large functions without any basic variation of the OBDD concept itself. The dynamic variable ordering with sifting introduced by Rudell [21] allows to represent examples which could not be represented by any previous heuristic methods. Moreover, the variable ordering in [21] is handled by the package itself, alleviating the need for variable ordering ...
On the Descriptive and Algorithmic Power of Parity Ordered Binary Decision Diagrams
 In Proc. of the 14th Symposium on Theoretical Aspects of Computer Science, volume 1200 of LNCS
, 1997
"... We present a data structure for Boolean functions, which we call ParityOBDDs or \Phi OBDDs, which combines the nice algorithmic properties of the wellknown ordered binary decision diagrams (OBDDs) with a considerably larger descriptive power. Beginning from an algebraic characterization of th ..."
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Cited by 18 (0 self)
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We present a data structure for Boolean functions, which we call ParityOBDDs or \Phi OBDDs, which combines the nice algorithmic properties of the wellknown ordered binary decision diagrams (OBDDs) with a considerably larger descriptive power. Beginning from an algebraic characterization of the \PhiOBDD complexity we prove in particular that the minimization of the number of nodes, the synthesis, and the equivalence test for \PhiOBDDs, which are the fundamental operations for circuit verification, have efficient deterministic solutions. Several functions of pratical interest, i.e. the indirect storage access function, have exponential ODBBsize but are of polynomial size if \PhiOBDDs are used. Keywords: data structures for Boolean functions, BDDs, circuit verification 1 Introduction Formal circuit verification is a fundamantal task. The following approach for verification is often used (for a survey see [8] and [21]). A data structure for representing Boolean functions is...
Equivalence Checking of Combinational Circuits using Boolean Expression Diagrams
 IEEE Transactions on Computer Aided Design
, 1999
"... The combinational logiclevel equivalence problem is to determine whether two given combinational circuits implement the same Boolean function. This problem arises in a number of CAD applications, for example when checking the correctness of incremental design changes (performed either manually or b ..."
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Cited by 16 (3 self)
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The combinational logiclevel equivalence problem is to determine whether two given combinational circuits implement the same Boolean function. This problem arises in a number of CAD applications, for example when checking the correctness of incremental design changes (performed either manually or by a design automation tool). This paper introduces a data structure called Boolean Expression Diagrams (BEDs) and two algorithms for transforming a BED into a Reduced Ordered Binary Decision Diagram (OBDD). BEDs are capable of representing any Boolean circuit in linear space and can exploit structural similarities between the two circuits that are compared. These properties make BEDs suitable for verifying the equivalence of combinational circuits. BEDs can be seen as an intermediate representation between circuits (which are compact) and OBDDs (which are canonical). Based on a large number of combinational circuits, we demonstrate that BEDs either outperform or achieve results comparable to...
Parallel BreadthFirst BDD Construction
 In Ninth ACM SIGPLAN Symposium on Principles and Practice of Parallel Programming
, 1997
"... With the increasing complexity of protocol and circuit designs, formal verification has become an important research area and binary decision diagrams (BDDs) have been shown to be a powerful tool in formal verification. This paper presents a parallel algorithm for BDD construction targeted at shared ..."
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Cited by 14 (2 self)
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With the increasing complexity of protocol and circuit designs, formal verification has become an important research area and binary decision diagrams (BDDs) have been shown to be a powerful tool in formal verification. This paper presents a parallel algorithm for BDD construction targeted at shared memory multiprocessors and distributed shared memory systems. This algorithm focuses on improving memory access locality through specialized memory managers and partial breadthfirst expansion, and on improving processor utilization through dynamic load balancing. The results on a shared memory system show speedups of over two on four processors and speedups of up to four on eight processors. The measured results clearly identify the main source of bottlenecks and point out some interesting directions for further improvements. 1 Introduction With the increasing complexity of protocol and circuit designs, formal verification has become an important research area. As an example, in 1994, In...
Formal Verification of WordLevel Specifications
, 1999
"... Formal verification has become one of the most important steps in circuit design. In this context the verification of highlevel Hardware Description Languages (HDLs), like VHDL, gets increasingly important. In this paper we present a complete set of datapath operations that can be formally verified ..."
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Cited by 13 (1 self)
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Formal verification has become one of the most important steps in circuit design. In this context the verification of highlevel Hardware Description Languages (HDLs), like VHDL, gets increasingly important. In this paper we present a complete set of datapath operations that can be formally verified based on WordLevel Decision Diagrams (WLDDs). Our techniques allow a direct translation of HDL constructs to WLDDs. We present new algorithms for WLDDs for modulo operation and division. These operations turn out to be the core of our efficient verification procedure. Furthermore, we prove upper bounds on the representation size of WLDDs guaranteeing effectiveness of the algorithms. Our verification tool is totally automatic and experimental results are given to demonstrate the efficiency of our approach. 1 Introduction Nowadays modern circuit design can contain several million transistors. For this, also verification of such large designs becomes more and more difficult, since pure simu...