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Symbolic Boolean manipulation with ordered binarydecision diagrams
 ACM COMPUTING SURVEYS
, 1992
"... Ordered BinaryDecision Diagrams (OBDDS) represent Boolean functions as directed acyclic graphs. They form a canonical representation, making testing of functional properties such as satmfiability and equivalence straightforward. A number of operations on Boolean functions can be implemented as grap ..."
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Cited by 1026 (13 self)
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Ordered BinaryDecision Diagrams (OBDDS) represent Boolean functions as directed acyclic graphs. They form a canonical representation, making testing of functional properties such as satmfiability and equivalence straightforward. A number of operations on Boolean functions can be implemented as graph algorithms on OBDD
Verification of Arithmetic Functions with Binary Moment Diagrams
 IN DESIGN AUTOMATION CONF
, 1994
"... Binary Moment Diagrams (BMDs) provide a canonical representations for linear functions similar to the way Binary Decision Diagrams (BDDs) represent Boolean functions. Within the class of linear functions, we can embed arbitary functions from Boolean variables to real, rational, or integer values. BM ..."
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Cited by 110 (6 self)
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Binary Moment Diagrams (BMDs) provide a canonical representations for linear functions similar to the way Binary Decision Diagrams (BDDs) represent Boolean functions. Within the class of linear functions, we can embed arbitary functions from Boolean variables to real, rational, or integer values. BMDs can thus model the functionality of data path circuits operating over word level data. Many important functions, including integer multiplication, that cannot be represented efficiently at the bit level with BDDs have simple representations at the word level with BMDs. Furthermore, BMDs can represent Boolean functions with around the same complexity as BDDs. We propose
Verification of Arithmetic Circuits with Binary Moment Diagrams
 IN PROCEEDINGS OF THE 32ND ACM/IEEE DESIGN AUTOMATION CONFERENCE
, 1995
"... Binary Moment Diagrams (BMDs) provide a canonical representations for linear functions similar to the way Binary Decision Diagrams (BDDs) represent Boolean functions. Within the class of linear functions, we can embed arbitrary functions from Boolean variables to integer values. BMDs can thus model ..."
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Cited by 108 (10 self)
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Binary Moment Diagrams (BMDs) provide a canonical representations for linear functions similar to the way Binary Decision Diagrams (BDDs) represent Boolean functions. Within the class of linear functions, we can embed arbitrary functions from Boolean variables to integer values. BMDs can thus model the functionality of data path circuits operating over wordlevel data. Many important functions, including integer multiplication, that cannot be represented efficiently at the bit level with BDDs have simple representations at the word level with BMDs. Furthermore, BMDs can represent Boolean functions with around the same complexity as BDDs. We propose a hierarchical approach to verifying arithmetic circuits, wherecomponentmodulesare first shownto implement their wordlevel specifications. The overall circuit functionality is then verified by composing the component functions and comparing the result to the wordlevel circuit specification. Multipliers with word sizes of up to 256 bits hav...
Binary decision diagrams in theory and practice
, 2001
"... Decision diagrams (DDs) are the stateoftheart data structure in VLSI CAD and have been successfully applied in many other fields.DDs are widely used and are also integrated in commercial tools.This special section comprises six contributed articles on various aspects of the theory and application ..."
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Cited by 31 (6 self)
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Decision diagrams (DDs) are the stateoftheart data structure in VLSI CAD and have been successfully applied in many other fields.DDs are widely used and are also integrated in commercial tools.This special section comprises six contributed articles on various aspects of the theory and application of DDs.As preparation for these contributions, the present article reviews the basic definitions of binary decision diagrams (BDDs). We provide a brief overview and study theoretical and practical aspects.Basic properties of BDDs are discussed and manipulation algorithms are described.Extensions of BDDs are investigated and by this we give a deeper insight into the basic data structure.Finally we outline several applications of BDDs and their extensions and suggest a number of articles and books for those who wish to pursue the topic in more depth.
Tearing Based Automatic Abstraction for CTL Model Checking
 IN ICCAD
, 1996
"... In this paper we present the tearing paradigm as a way to automatically abstract behavior to obtain upper and lower bound approximations of a reactive system. We present algorithms that exploit the bounds to perform conservative ECTL and ACTL model checking. We also give an algorithm for false neg ..."
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Cited by 30 (2 self)
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In this paper we present the tearing paradigm as a way to automatically abstract behavior to obtain upper and lower bound approximations of a reactive system. We present algorithms that exploit the bounds to perform conservative ECTL and ACTL model checking. We also give an algorithm for false negative (or false positive) resolution for verification based on a theory of a lattice of approximations. We show that there exists a bipartition of the lattice set based on positive versus negative verification results. Our resolution methods are based on determining a pseudooptimal shortest path from a given, possibly coarse but tractable approximation, to a nearest point on the contour separating one set of the bipartition from the other.
How Many Decomposition Types Do We Need
 In European Design and Test Conference (EDTC
, 1995
"... Decision Diagrams (DDs) are used in many applications in CAD. Various types of DDs, e.g. BDDs, FDDs, KFDDs, di er by their decomposition types. In this paper we investigate the di erent decomposition types and prove that there are only three that really help to reduce the size of DDs. 1 ..."
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Cited by 24 (6 self)
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Decision Diagrams (DDs) are used in many applications in CAD. Various types of DDs, e.g. BDDs, FDDs, KFDDs, di er by their decomposition types. In this paper we investigate the di erent decomposition types and prove that there are only three that really help to reduce the size of DDs. 1
Efficient Construction of Binary Moment Diagrams for Verifying Arithmetic Circuits
, 1995
"... Binary Decision Diagrams (BDDs) have been used as a very powerful tool for manipulating Boolean functions in various application domains, in particular, design verification of logic circuits. We can representmany practical functions with reasonable size of BDDs, and perform Boolean operations very e ..."
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Cited by 23 (0 self)
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Binary Decision Diagrams (BDDs) have been used as a very powerful tool for manipulating Boolean functions in various application domains, in particular, design verification of logic circuits. We can representmany practical functions with reasonable size of BDDs, and perform Boolean operations very efficiently. Unfortunately, the sizes of the BDDs for representing multiplication are known to blow up exponentially to the number of inputs. Binary Moment Diagrams (BMDs) are graph representations of mappings from binary vectors to integers. BMDs also provide canonical representations to those functions. When we use BMDs, we can represent the output function at the word level. We can represent the functions expressing multiplication with BMDs whose size grows only linearly with the number of variables. Bryant and Chen reported a BMDbased polynomialtime algorithm for verifying multipliers. This approach requires highlevel information such as specifications to subcomponents. From users' point of view, it is convenient to handle circuit descriptions without giving specifications to subcomponents. This paper presents a new technique called backward sweeping. Using this technique, we can verify arithmetic circuits without any highlevel information. Although our experiments are preliminary, the results for array multipliers and Wallacetree multipliers both show that the order of the computation time is approximately n 3:5, where n is the number of inputs. We have successfully veri ed 31bit Wallacetree multipliers in 260 seconds with 3 Mbyte of memory on SPARCstation10/51. We have also built the BMD for c6288 in 72 seconds with 2Mbyte of memory. This result outperforms previous BDDbased approaches for verifying multipliers.
Logic Design Error Diagnosis and Correction
 IEEE Transactions on VLSI Systems
, 1994
"... She's the neighbor dog who's courting my dog. ..."
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Cited by 22 (3 self)
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She's the neighbor dog who's courting my dog.
Exploiting Structural Similarities in a BDDbased Verification Method
 in Theorem Provers in Circuit Design. 1994, number 901 in Lecture Notes in Computer Science
, 1994
"... . A major challenge in the area of hardware verification is to devise methods that can handle circuits of practical size. This paper intends to show how the applicability of combinational circuit verification tools based on binary decision diagrams (BDDs) can be greatly improved. The introduction of ..."
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Cited by 13 (1 self)
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. A major challenge in the area of hardware verification is to devise methods that can handle circuits of practical size. This paper intends to show how the applicability of combinational circuit verification tools based on binary decision diagrams (BDDs) can be greatly improved. The introduction of dynamic variable ordering techniques already makes these tools more robust; a designer no longer needs to worry about a good initial variable order. In addition, we present a novel approach combining BDDs with a technique that exploits structural similarities of the circuits under comparison. We explain how these similarities can be detected and put to effective use in the verification process. Benchmark results show that the proposed method significantly extends the range of circuits that can be verified using BDDs. 1 Introduction The times when researchers in the CAD field could sit in their ivory tower thinking up neat solutions for theoretical problems belong to the past. Nowadays, ind...
*BMDs Can Delay the Use of Theorem Proving for Verifying Arithmetic Assembly Instructions
 IN FMCAD
, 1996
"... We address the problem of formally verifying arithmetic instructions of microprocessors implemented by microprograms that contain loops. We try to avoid theorem proving techniques using a new symbolic representation: Binary Moment Diagrams (*BMDs). In order to use *BMDs for verifying sequential circ ..."
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Cited by 10 (0 self)
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We address the problem of formally verifying arithmetic instructions of microprocessors implemented by microprograms that contain loops. We try to avoid theorem proving techniques using a new symbolic representation: Binary Moment Diagrams (*BMDs). In order to use *BMDs for verifying sequential circuits as well as microprograms, we extend this representation and define several bitvector level operators. This extension is then integrated into an automatic verification system. We illustrate the paper with examples and we discuss power and weakness of *BMDs.