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Design of Dynamically Reconfigurable RealTime Software using PortBased Objects
, 1993
"... a "oneofakind" process, where most software is developed from scratch, even though much of the code is similar to code written for other applications. The cost of these systems can be drastically reduced and the capability of these systems improved by providing a suitable software fram ..."
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Cited by 137 (18 self)
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a "oneofakind" process, where most software is developed from scratch, even though much of the code is similar to code written for other applications. The cost of these systems can be drastically reduced and the capability of these systems improved by providing a suitable software framework for all R&A sys~ terns, We describe a novel software framework, based on the notion of dynamically reconfigurable software for sensorbased control systems. Tools to support the implementation of this framework have been built into the Chimera 3.0 RealTime Operating System. The framework provides for the systematic development and predictable execution of flexible R&A applications while maintaining the ability to reuse code f)om previous applications. It combines objectoriented design of software with portautomaton design of digital control systems. A control module is an instance of a class of portbased objects. A task set is formed by integrating objects from a module library to form a specific configuration. An implementation using global state variables for the automatic integration of portbased objects is presented. A control subsystem is a collection of jobs which are executed one at a time, and can be programmed by a user. Multiple control subsystems can execute in parallel, and operate either independently or cooperatively. One of the fundamental concepts of reconfigurable software design is that modules are developed independent of the target hard ware. Our framework defines classes of reconfigurable device driver objects for proving hardware independence to IJO devices, sensors, actuators, and special purpose processors. Hardware independent realtime communication mechanisms for intersubsystem eommurtication are also described. A/ong with providing a foundatio...
Synthesis Of Embedded Software From Synchronous Dataflow Specifications
 JOURNAL OF VLSI SIGNAL PROCESSING SYSTEMS
, 1999
"... The implementation of software for embedded digital signal processing (DSP) applications is an extremely complex process. The complexity arises from escalating functionality in the applications; intense timetomarket pressures; and stringent cost, power and speed constraints. To help cope with such ..."
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Cited by 79 (15 self)
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The implementation of software for embedded digital signal processing (DSP) applications is an extremely complex process. The complexity arises from escalating functionality in the applications; intense timetomarket pressures; and stringent cost, power and speed constraints. To help cope with such complexity, DSP system designers have increasingly been employing highlevel, graphical design environments in which system specification is based on hierarchical dataflow graphs. Consequently, a significant industry has emerged for the development of dataflow based DSP design environments. Leading products in this industry include SPW from Cadence, COSSAP from Synopsys, ADS from Hewlett Packard, and DSP Station from Mentor Graphics. This paper reviews a set of algorithms for compiling dataflow programs for embedded DSP applications into efficient implementations on programmable digital signal processors. The algorithms focus primarily on the minimization of code size, and the minimization of the memory required for the buffers that implement the communication channels in the input dataflow graph. These are critical problems because programmable digital signal processors have very limited amounts of onchip memory, and the speed, power, and cost penalties for using offchip memory are often prohibitively high for embedded applications. Furthermore, memory demands of applications are increasing at a significantly higher rate than the rate of increase in onchip memory capacity offered by improved integrated circuit technology.
Multidimensional Synchronous Dataflow
 IEEE Transactions on Signal Processing
, 2002
"... Signal flow graphs with dataflow semantics have been used in signal processing system simulation, algorithm development, and realtime system design. Dataflow semantics implicitly expose function parallelism by imposing only a partial ordering constraint on the execution of functions. One particular ..."
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Cited by 51 (4 self)
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Signal flow graphs with dataflow semantics have been used in signal processing system simulation, algorithm development, and realtime system design. Dataflow semantics implicitly expose function parallelism by imposing only a partial ordering constraint on the execution of functions. One particular form of dataflow called synchronous dataflow (SDF) has been quite popular in programming environments for digital signal processing (DSP) since it has strong formal properties and is ideally suited for expressing multirate DSP algorithms. However, SDF and other dataflow models use firstin firstout (FIFO) queues on the communication channels and are thus ideally suited only for onedimensional (1D) signal processing algorithms. While multidimensional systems can also be expressed by collapsing arrays into 1D streams, such modeling is often awkward and can obscure potential data parallelism that might be present. SDF can be generalized...
Static scheduling and code generation from dynamic dataflow graphs with integervalued control streams
 In Proceedings of the 28th Annual Asilomar Conference on Signals, Systems, and Computers
, 1994
"... This paper extends the token flow model of Buck and Lee ([1],[2]), an analytical model for the behavior of dataflow graphs with datadependent control flow, in two ways: dataflow actor execution may depend on integer, rather than Boolean, control tokens, and multiphase implementations of actors are ..."
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Cited by 49 (0 self)
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This paper extends the token flow model of Buck and Lee ([1],[2]), an analytical model for the behavior of dataflow graphs with datadependent control flow, in two ways: dataflow actor execution may depend on integer, rather than Boolean, control tokens, and multiphase implementations of actors are permitted. These extensions permit datadependent iteration to be modelled more naturally, reduce the memory required for implementations, and result in boundedmemory solutions in more cases than before. A method for generating efficient singleprocessor programs from the graphs is also described. 1. Introduction and
APGAN and RPMC: Complementary Heuristics for Translating DSP Block Diagrams into Efficient Software Implementations
 DSP BLOCK DIAGRAMS INTO EFFICIENT SOFTWARE IMPLEMENTATIONS”, DAES
, 1997
"... Dataflow has proven to be an attractive computational model for graphical DSP design environments that support the automatic conversion of hierarchical signal flow diagrams into implementations on programmable processors. The synchronous dataflow (SDF) model is particularly wellsuited to dataflowba ..."
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Cited by 45 (10 self)
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Dataflow has proven to be an attractive computational model for graphical DSP design environments that support the automatic conversion of hierarchical signal flow diagrams into implementations on programmable processors. The synchronous dataflow (SDF) model is particularly wellsuited to dataflowbased graphical programming because its restricted semantics offer strong formal properties and significant compiletime predictability, while capturing the behavior of a large class of important signal processing applications. When synthesizing software for embedded signal processing applications, critical constraints arise due to the limited amounts of memory. In this paper, we propose a solution to the problem of jointly optimizing the code and data size when converting SDF programs into software implementations. We consider two approaches. The first is a customization to acyclic graphs of a bottomup technique, called pairwise grouping of adjacent nodes (PGAN), that was proposed earlier f...
Hierarchical static scheduling of dataflow graphs onto multiple processors
 IEEE International Conference on Acoustics, Speech, and Signal Processing
, 1995
"... In this paper we discuss a hierarchical scheduling framework to reduce the complexity of scheduling synchronous dataflow (SDF) graphs onto multiple processors. The core of this framework is a clustering technique that reduces the number of actors before expanding the SDF graph into an directed acycl ..."
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Cited by 31 (5 self)
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In this paper we discuss a hierarchical scheduling framework to reduce the complexity of scheduling synchronous dataflow (SDF) graphs onto multiple processors. The core of this framework is a clustering technique that reduces the number of actors before expanding the SDF graph into an directed acyclic graph (DAG). The internals of the clusters are then scheduled with uniprocessor SDF schedulers which can optimize for memory usage. The clustering is done in such a manner as to leave ample parallelism exposed for the multiprocessor scheduler. We illustrate this framework with a realtime example that has been constructed in Ptolemy. 1.
Generating Compact Code From Dataflow Specifications Of Multirate Signal Processing Algorithms
 IEEE TRANSACTIONS ON CIRCUITS AND SYSTEMS — I: FUNDAMENTAL THEORY AND APPLICATIONS
, 1995
"... Synchronous dataflow (SDF) semantics are wellsuited to representing and compiling multirate signal processing algorithms. A key to this match is the ability to cleanly express iteration without overspecifying the execution order of computations, thereby allowing efficient schedules to be constructe ..."
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Cited by 31 (16 self)
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Synchronous dataflow (SDF) semantics are wellsuited to representing and compiling multirate signal processing algorithms. A key to this match is the ability to cleanly express iteration without overspecifying the execution order of computations, thereby allowing efficient schedules to be constructed. Due to limited program memory, it is often desirable to translate the iteration in an SDF graph into groups of repetitive firing patterns so that loops can be constructed in the target code. This paper establishes fundamental topological relationships between iteration and looping in SDF graphs, and presents a scheduling framework that provably synthesizes the most compact looping structures for a large class of practical SDF graphs. By modularizing different components of the scheduling framework, and establishing their independence, we show how other scheduling objectives, such as minimizing data buffering requirements or increasing the number of data transfers that occur in registers, ...
Minimizing Memory Requirements in RateOptimal Schedules
, 1994
"... In this paper we address the problem of minimizing buffer storage requirement in constructing rateoptimal compiletime schedules for multirate dataflow graphs. We demonstrate that this problem, called the Minimum Buffer RateOptimal (MBRO) scheduling problem, can be formulated as a unified linear ..."
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Cited by 30 (2 self)
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In this paper we address the problem of minimizing buffer storage requirement in constructing rateoptimal compiletime schedules for multirate dataflow graphs. We demonstrate that this problem, called the Minimum Buffer RateOptimal (MBRO) scheduling problem, can be formulated as a unified linear programming problem. A novel feature of our method is that it tries to minimize the memory requirement while simultaneously maximizing the computation rate. We have constructed an experimental testbed which implements our scheduling algorithm as well as (i) the widely used periodic admissible parallel schedules proposed by Lee and Messerschmitt [12], (ii) the optimal scheduling buffer allocation (OSBA) algorithm of Ning and Gao [15], and (iii) the multirate software pipelining (MRSP) algorithm [7]. The experimental results have demonstrated a significant improvement in buffer requirements for the MBRO schedules compared to the schedules generated by the other three methods. Compared to bloc...
Joint minimization of code and data for synchronous dataflow programs
 J. Formal Methods Syst. Des
, 1997
"... Abstract. In this paper, we formally develop techniques that minimize the memory requirements of a target program when synthesizing software from dataflow descriptions of multirate signal processing algorithms. The dataflow programming model that we consider is the synchronous dataflow (SDF) model [ ..."
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Cited by 29 (4 self)
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Abstract. In this paper, we formally develop techniques that minimize the memory requirements of a target program when synthesizing software from dataflow descriptions of multirate signal processing algorithms. The dataflow programming model that we consider is the synchronous dataflow (SDF) model [21], which has been used heavily in DSP design environments over the past several years. We first focus on the restricted class of wellordered SDF graphs. We show that while extremely efficient techniques exist for constructing minimum code size schedules for wellordered graphs, the number of distinct minimum code size schedules increases combinatorially with the number of vertices in the input SDF graph, and these different schedules can have vastly different data memory requirements. We develop a dynamic programming algorithm that computes the schedule that minimizes the data memory requirement from among the schedules that minimize code size, and we show that the time complexity of this algorithm is cubic in the number of vertices in the given wellordered SDF graph. We present several extensions to this dynamic programming technique to more general scheduling problems, and we present a heuristic that often computes nearoptimal schedules with quadratic time complexity. We then show that finding optimal solutions for arbitrary acyclic graphs is NPcomplete, and present heuristic techniques that jointly minimize code and data size requirements. We present a practical example and simulation data that demonstrate the effectiveness of these techniques.
Software Synthesis and Code Generation for Signal Processing Systems
, 2000
"... The role of software is becoming increasingly important in the implementation of DSP applications. As this trend intensifies, and the complexity of applications escalates, we are seeing an increased need for automated tools to aid in the development of DSP software. This paper reviews the state of t ..."
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Cited by 25 (4 self)
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The role of software is becoming increasingly important in the implementation of DSP applications. As this trend intensifies, and the complexity of applications escalates, we are seeing an increased need for automated tools to aid in the development of DSP software. This paper reviews the state of the art in programming language and compiler technology for DSP software implementation. In particular, we review techniques for high level, blockdiagrambased modeling of DSP applications; the translation of block diagram specifications into efficient C programs using global, targetindependent optimization techniques; and the compilation of C programs into streamlined machine code for programmable DSP processors, using architecturespecific and retargetable backend optimizations. We also point out important directions for further investigation.