Programmable processors offer a high degree of flexibility and are therefore increasingly being used in embedded systems. We introduce the formalism nML which is especially suited to describe such processors in terms of their instruction set, an nML description is directly related to the standard description as found in the usual programmer's manuals. The nML formalism is based on a mixed structural and behavioural model facilitating exact yet concise descriptions. The philosophy of nML is already applied in two approaches to retargetable code generation and instruction set simulation. 1 Introduction In consumer electronics and telecommunications high product volumes are increasingly combined with short life-times and high system complexity. The pressure on development times together with the demand to react on late specification changes make mask or field programmability a desired feature. The thereby obtained flexibility not only helps to shorten the design cycle, but also allows fo...

The role of software is becoming increasingly important in the implementation of DSP applications. As this trend intensifies, and the complexity of applications escalates, we are seeing an increased need for automated tools to aid in the development of DSP software. This paper reviews the state of the art in programming language and compiler technology for DSP software implementation. In particular, we review techniques for high level, block-diagram-based modeling of DSP applications; the translation of block diagram specifications into efficient C programs using global, target-independent optimization techniques; and the compilation of C programs into streamlined machine code for programmable DSP processors, using architecture-specific and retargetable back-end optimizations. In our review, we also point out some important directions for further investigation.

this article, we trace the evolution of DSP processors, from early architectures to current state-of-the-art devices. We highlight some of the key differences among architectures, and compare their strengths and weaknesses. Finally, we discuss the growing class of generalpurpose processors that have been enhanced to address the needs of DSP applications

Scheduling is an essential task both in high-level synthesis and in code generation for programmable processors. In this paper we discuss the impact of the controller model on the scheduling task for DSP applications. Existing techniques in high-level synthesis mostly assume a simple controller model in the form of a single FSM. However, in reality more complex controller architectures are often used. On the other hand, in the case of programmable processors, the controller architecture is largely defined by the available control-flow instructions in the instruction set. In this paper, a unified scheduling model is presented to handle a wide range of controller architectures, from the applicationspecific to programmableprocessorsolutions. Theimpact of chosing a certain controller architecture on the scheduling phase is investigated. Finally, the tasks of controller generation and code assembly are discussed, which will generate the FSM or machine code description from the correct sche...

This paper presents an efficient method for implementation of digital filters targeted FPGA architectures. The traditional approach is based on application of general purpose multipliers. However, performance of multipliers implemented in FPGA architectures does not allow to constructs high performance digital filters. In this paper application of distributed arithmetic is demonstrated. Since in this approach general purpose multipliers are replaced by combinational LUT blocks, it is possible to construct digital filters of very high performance. However LUT blocks can be of considerable size thus advanced synthesis methods have to be used to map them efficiently into FPGA resources. In this paper an application of the functional decomposition based synthesis has been investigated. This method is recognised as the best synthesis method targeted FPGA architectures and allows significant improvements in digital filters implementation. The paper presents many examples confirming that decomposition allows reduction of logic cell utilisation of filter implementation based on distributed arithmetic concept with no performance degradation and even increasing it.

Introduction P. Marwedel 1 New, flexible target technologies As the tendency towards more complex electronic systems continues, many of these systems are equipped with embedded processors. For example, such processors can be found in cars, and in audio-, video-, and telecommunication-equipment. Essential advantages of these processors include their high flexibility, short design time and (in the case of off-the-shelf processors) full-custom layout quality. Furthermore, they allow an easy implementation of optional product features as well as easy design correction and upgrading. Furthermore, processors are frequently used in cases where the systems must be extremely dependable 1 [32]. In such cases, the re-use of the design of an off-the-shelf processor greatly simplifies dependability analysis. This contrasts with the limitations of application-specific circuits (ASICs): due to their low flexibility, the cost for the desig

This tutorial responds to the rapidly increasing use of various cores for implementing systems-on-a-chip. It specifically focusses on processor cores. We will give some examples of cores, including DSP cores and application-specific instruction-set processors (ASIPs). We will mention market trends for these components, and we will touch design procedures, in particular the use compilers. Finally, we will discuss the problem of testing corebased designs. Existing solutions include boundary scan, embedded in-circuit emulation (ICE), the use of processor resources for stimuli/response compaction and self-test programs. I. Introduction In response to the increasing size of advanced chips and the continuing need for fast design cycles, a major amount of new designs is using complex cores (rather than standard cells and macroblocks) as building blocks. Such cores include: processor cores, communication cores, bus interface cores, and memory cores. These cores are available both from vendors...

Digital signal processors (DSPs) have been used to realize real-time signal processing systems using hardware architectures and software instruction sets that are optimized for such applications. However, general-purpose microprocessors have risen in capability to the point that they can serve as alternative platforms for digital signal processing applications, particularly for audiorate systems. This paper compares the capabilities of two general-purpose microprocessors-- the Apple/IBM/Motorola PowerPC 604 and Intel Pentium P5--with the popular Texas Instruments' TMS320C40 DSP on a suite of three common signal processing subsystems: i) a finite-impulse-response (FIR) filter, ii) the least-mean-square (LMS) adaptive filter, and iii) the fast Fourier transform (FFT). Careful attention is paid to the architectures of the processors to obtain the most computationallyefficient realizations. The results indicate that general-purpose microprocessors are viable computational engines for audio...

The successive doubling method is an ecient procedure for the design of fast algorithms for orthogonal transforms of length N = r n , where the radix r is a power of 2. It reduces the algorithmic complexity from N 2 to N log r N . In this work we present a partitioned systolic architecture for the two standard radix successive doubling algorithms: ascend and descend communication patterns. The systolization and partitioning procedure we have used is made up of three actions. First, we transform the ow chart of the data for the successive doubling algorithm into a new chart of constant geometry in all its stages (n). We obtain the constant geometry by means of the perfect unshue (ascending algorithm) or shuf- e (descending algorithm) permutations of order log 2 r. We then carry out the decomposition of these permutations into elementary permutations, which can be implemented electronically. Finally, we project the index space of the data onto the index space associ...

This tutorial responds to the rapidly increasing use of cores in general and of processor cores in particular for implementing systems-on-a-chip. In the first part of this text, we will provide a brief introduction to various cores. Applications can be found in most segments of the embedded systems market. These applications demand for extreme efficiency, and in particular for efficient processorarchitecturesand for efficient embedded software. In the second part of this text, we will show that current compilers do not provide the required efficiency and we will give an overview over new compiler optimization techniques,which aim at making assembly language programming for embedded software obsolete. Thesenew techniquestake advantageof the special characteristics of embedded software and embedded architectures. Due to efficiency considerations, processorarchitecturesoptimized for application domains or even for particular applications are of interest. This results in a large number of ...