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In the context of developing a compiler for a Alpha, a functional dataparallel language based on systems of affine recurrence equations (SAREs), we address the problem of transforming scheduled single-assignment code to multiple assignment code. We show how the polyhedral model allows us to statically compute the lifetimes of program variables, and thus enables us to derive necessary and sufficient conditions for reusing memory. 1. Introduction The methodology of automatic systolic array synthesis from Systems of Affine Recurrence Equations (SAREs) has a close bearing on parallelizing compilers and on efficient implementation of functional languages. To study this relationship, we are currently developing a compiler for Alpha [9], a functional, data parallel language based on SAREs defined over polyhedral index domains. The language semantics directly lead to sequential code based on demand driven evaluation. However, the resulting context switches can be avoided if the program is tra...

Abstract—The design of complex Systems-on-Chips implies to take into account communication and memory access constraints for the integration of dedicated hardware accelerator. In this paper, we present a methodology and a tool that allow the High-Level Synthesis of DSP algorithm, under both I/O timing and memory constraints. Based on formal models and a generic architecture, this tool helps the designer to find a reasonable trade-off between both the required I/O timing behavior and the internal memory access parallelism of the circuit. The interest of our approach is demonstrated on the case study of a FFT algorithm. I.

The novel optimization technique for the design of application specific integrated circuits of multi-dimensional problems, called multi-dimensional interleaving consists of an expansion and compression of the iteration space. It guarantees that all functional elements of a circuitry can be executed simultaneously, and no additional memory queues proportional to the problem size are required. Such technique, that considers the parallelism inherent to multi-dimensional problems, depend on loop transformations that require a new execution sequence of the loop. This study presents a new approach on synthesizing multidimensional (nested) loops, where pre-processor tools can rewrite the instructions in such a way to accomodate the required changes in the optimized design. This new approach is expected to improve the design cycle by including multidimensional signal processing and other common applications in the scope of the synthesis tools.

This paper presents new results for formal verification of loop transformations applied on complex applications in the area of speech, image and video processing, front-end telecom and numerical computing systems. The