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Verification Tools for FiniteState Concurrent Systems
"... Temporal logic model checking is an automatic technique for verifying finitestate concurrent systems. Specifications are expressed in a propositional temporal logic, and the concurrent system is modeled as a statetransition graph. An efficient search procedure is used to determine whether or not t ..."
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Cited by 129 (3 self)
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Temporal logic model checking is an automatic technique for verifying finitestate concurrent systems. Specifications are expressed in a propositional temporal logic, and the concurrent system is modeled as a statetransition graph. An efficient search procedure is used to determine whether or not the statetransition graph satisfies the specification. When the technique was first developed ten years ago, it was only possible to handle concurrent systems with a few thousand states. In the last few years, however, the size of the concurrent systems that can be handled has increased dramatically. By representing transition relations and sets of states implicitly using binary decision diagrams, it is now possible to check concurrent systems with more than 10 120 states. In this paper we describe in detail how the new implementation works and
A language for compositional specification and verification of finite state hardware controllers
 Proceedings of the IEEE
, 1991
"... Abstract SML is a language for describing complex finitestate hardware controllers. It provides many of the standard control structures found in modern programming languages. The state tables produced by the SML compiler can be used as input to a temporal logic model checker that can automatically ..."
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Cited by 38 (2 self)
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Abstract SML is a language for describing complex finitestate hardware controllers. It provides many of the standard control structures found in modern programming languages. The state tables produced by the SML compiler can be used as input to a temporal logic model checker that can automatically determine whether a specification in the logic CTL is satisfied. We describe extensions to SML for the design of modular controllers. These extensions allow a compositional approach to model checking which can substantially reduce its complexity. To demonstrate our methods, we discuss the specification and verification of a simple CPU controller. 0
Automatic distribution of reactive systems for asynchronous networks of processors
 IEEE Transactions on Software Engineering
, 1999
"... Abstract—This paper addresses the problem of automatically distributing reactive systems. We first show that the use of synchronous languages allows a natural parallel description of such systems, regardless of any distribution problems. Then, a desired distribution can be easily specified, and achi ..."
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Cited by 33 (7 self)
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Abstract—This paper addresses the problem of automatically distributing reactive systems. We first show that the use of synchronous languages allows a natural parallel description of such systems, regardless of any distribution problems. Then, a desired distribution can be easily specified, and achieved with the algorithm presented here. This distribution technique provides distributed programs with the same safety, test, and debug facilities as ordinary sequential programs. Finally, the implementation of such distributed programs only requires a very simple communication protocol (“first in first out ” queues), thereby reducing the need for large distributed realtime executives. Index Terms—Asynchronous communications, distributed processing, reactive systems, automatic distribution, synchronous languages. ————————— — F ——————————
Distributing Reactive Systems
, 1994
"... This paper addresses the problem of distributing reactive systems. We first show that the use of synchronous languages allows a natural parallel description of such systems, regardless of any distribution problems. Then, a desired distribution can be easily specified, and achieved with the algorithm ..."
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Cited by 21 (4 self)
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This paper addresses the problem of distributing reactive systems. We first show that the use of synchronous languages allows a natural parallel description of such systems, regardless of any distribution problems. Then, a desired distribution can be easily specified, and achieved with the algorithm presented here. This distribution technique provides distributed programs with the same safety, test and debug facilities as ordinary sequential programs. Finally, the implementation of such distributed programs only requires a very simple communication protocol ("first in first out" queues), thereby reducing the need for large distributed realtime executives.
Software Implementation of Synchronous Programs
 In Proceedings of the Second International Conference on Application of Concurrency to System Design, Newcastle upon Tyne
, 2001
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Formale Verifikation eingebetteter Systeme. Informationstechnik und Technische Informatik (it+ti
, 1999
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Ordered Ternary Decision Diagrams and the Multivalued Compiled Simulation of Unmapped Logic
 Proc. IEEE 27th Annual Simulation Symposium
, 1994
"... We describe a method for generating logic simulation code which correctly responds to any number of undefined logic values at the code inputs. The method is based on our development of the Ordered Ternary Decision Diagram, itself based on Kleenean ternary logic, which explicitly and correctly manage ..."
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Cited by 2 (0 self)
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We describe a method for generating logic simulation code which correctly responds to any number of undefined logic values at the code inputs. The method is based on our development of the Ordered Ternary Decision Diagram, itself based on Kleenean ternary logic, which explicitly and correctly manages the unknown logic value `U' in addition to the `1' and `0' of conventional OBDDs. We describe the OTDD and how to implement its reduction, application, and restriction operations. This method avoids expensive technology mapping, producing highly efficient `U'correct compiled logic simulation code in seconds rather than in hours. Our experiments toward confirming the validity of the method are reported.
Model Checking: Historical Perspective and Example (Extended Abstract)
 TABLEAUX'98
, 1998
"... Model checking is an automatic verification technique for finite state concurrent systems such as sequential circuit designs and communication protocols. Specifications are expressed in propositional temporal logic. An exhaustive search of the global state transition graph or system model is u ..."
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Cited by 1 (0 self)
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Model checking is an automatic verification technique for finite state concurrent systems such as sequential circuit designs and communication protocols. Specifications are expressed in propositional temporal logic. An exhaustive search of the global state transition graph or system model is used to determine if the specification is true or not. If the
POLLUX: A LUSTRE based hardware design environment
, 1994
"... This paper presents a highlevel hardware design environment called Pollux. A design description is written with the Lustre dataflow language, and used by the different Pollux tools to produce the corresponding synchronous circuit or, for example, a simulation program, that can be compiled and e ..."
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This paper presents a highlevel hardware design environment called Pollux. A design description is written with the Lustre dataflow language, and used by the different Pollux tools to produce the corresponding synchronous circuit or, for example, a simulation program, that can be compiled and executed on a sequential machine. Lustre has been chosen because it is wellsuited to hardware description, but it has also been extended to become a full synchronous hardware description language. The first extension allows the description of a floorplan to be included in a Lustre program. Other extensions (arrays, recursion or parameterized subprograms) have been introduced in order to make simpler the description of large designs, without loosing the primitive advantages of the language, especially precision and clarity. The circuits generated by Pollux are currently used to configure a Programmable Active Memory, where they can be executed. 1 Introduction The range of applicatio...