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16
Performance optimization of VLSI interconnect layout
 Integration, the VLSI Journal
, 1996
"... This paper presents a comprehensive survey of existing techniques for interconnect optimization during the VLSI physical design process, with emphasis on recent studies on interconnect design and optimization for highperformance VLSI circuit design under the deep submicron fabrication technologies. ..."
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Cited by 104 (32 self)
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This paper presents a comprehensive survey of existing techniques for interconnect optimization during the VLSI physical design process, with emphasis on recent studies on interconnect design and optimization for highperformance VLSI circuit design under the deep submicron fabrication technologies. First, we present a number of interconnect delay models and driver/gate delay models of various degrees of accuracy and efficiency which are most useful to guide the circuit design and interconnect optimization process. Then, we classify the existing work on optimization of VLSI interconnect into the following three categories and discuss the results in each category in detail: (i) topology optimization for highperformance interconnects, including the algorithms for total wire length minimization, critical path length minimization, and delay minimization; (ii) device and interconnect sizing, including techniques for efficient driver, gate, and transistor sizing, optimal wire sizing, and simultaneous topology construction, buffer insertion, buffer and wire sizing; (iii) highperfbrmance clock routing, including abstract clock net topology generation and embedding, planar clock routing, buffer and wire sizing for clock nets, nontree clock routing, and clock schedule optimization. For each method, we discuss its effectiveness, its advantages and limitations, as well as its computational efficiency. We group the related techniques according to either their optimization techniques or optimization objectives so that the reader can easily compare the quality and efficiency of different solutions.
PerformanceDriven Interconnect Design Based on Distributed RC Delay Model
 in Proc. Design Automation Conf
, 1993
"... In this paper, we study the interconnect design problem under a distributed RC delay model. We study the impact of technology factors on the interconnect designs and present general formulations of the interconnect topology design and wiresizing problems. We show that interconnect topology optimizat ..."
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Cited by 68 (21 self)
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In this paper, we study the interconnect design problem under a distributed RC delay model. We study the impact of technology factors on the interconnect designs and present general formulations of the interconnect topology design and wiresizing problems. We show that interconnect topology optimization can be achieved by computing optimal generalized rectilinear Steiner arborescences and we present an efficient algorithm which yields optimal or nearoptimal solutions. We reveal several important properties of optimal wire width assignments and present a polynomial time optimal wiresizing algorithm. Extensive experimental results indicate that our approach significantly outperforms other routing methods for highperformance IC and MCM designs. Our interconnect designs reduce the interconnection delays by up to 66% as compared to those by the best known Steiner tree algorithm. 1 Introduction As the VLSI fabrication technology reaches submicron device dimension and gigahertz frequency, ...
Balancing Minimum Spanning and Shortest Path Trees
, 1993
"... Efficient algorithms are known for computing a minimum spann.ing tree, or a shortest path. tree (with a fixed vertex as the root). The weight of a shortest path tree can be much more than the weight of a minimum spa,nning tree. Conversely, the distance bet,ween the root, and any vertex in a minimum ..."
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Cited by 64 (1 self)
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Efficient algorithms are known for computing a minimum spann.ing tree, or a shortest path. tree (with a fixed vertex as the root). The weight of a shortest path tree can be much more than the weight of a minimum spa,nning tree. Conversely, the distance bet,ween the root, and any vertex in a minimum spanning tree may be much more than the distance bet#ween the two vertices in the graph. Consider the problem of balancing between the two kinds of trees: Does every graph contain a tree that is “light ” (at most a constant times heavier than the minimum spanning t,ree), such that the distance from the root to any vertex in t,he tree is no more than a constant times the true distance? This paper answers the question in the affirmative. It is shown that there is a continuous tradeoff between the two parameters. For every y> 0, there is a tree in the graph whose total weight is at most 1 + $? times the weight of a minimum spanning tree, such that the di&nce in the tree between the root, and any vertex is at, most 1 + &y times the true distance. Efficient sequential and parallel algorithms achieving these factors are provided. The algorithms are shown to be optimal in two ways. First, it is shown that no algorithm can achieve better factors in all graphs, because there a.re graphs that do not have better trees. Second, it is shown that even on a pergraph basis, finding trees that achieve better factors is NPhard.
HighPerformance Routing Trees With Identified Critical Sinks
, 1992
"... We present two criticalsink routing tree (CSRT) constructions which exploit criticalpath information that becomes available during timingdriven layout. Our CSSteiner heuristics with "Global Slack Removal" modify traditional Steiner constructions and produce routing trees with significa ..."
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Cited by 39 (13 self)
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We present two criticalsink routing tree (CSRT) constructions which exploit criticalpath information that becomes available during timingdriven layout. Our CSSteiner heuristics with "Global Slack Removal" modify traditional Steiner constructions and produce routing trees with significantly lower criticalsink delays compared with existing performancedriven methods. We also propose a new class of Elmore routing tree (ERT) constructions, which iteratively add tree edges to minimize Elmore delay. This direct optimization of Elmore delay yields trees that improve delays to identified critical sinks by up to 69 % over minimum Steiner routings. ERTs also improve performance over such recent methods as [1] [6] when no critical sinks are specified.
Balancing Minimum Spanning Trees and ShortestPath Trees
, 2002
"... We give a simple algorithm to find a spanning tree that simultaneously approximates a shortestpath tree and a minimum spanning tree. The algorithm provides a continuous tradeoff: given the two trees and a fl? 0, the algorithm returns a spanning tree in which the distance between any vertex and the ..."
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Cited by 38 (1 self)
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We give a simple algorithm to find a spanning tree that simultaneously approximates a shortestpath tree and a minimum spanning tree. The algorithm provides a continuous tradeoff: given the two trees and a fl? 0, the algorithm returns a spanning tree in which the distance between any vertex and the root of the shortestpath tree is at most 1 + p 2fl times the shortestpath distance, and yet the total weight of the tree is at most 1 + p 2=fl times the weight of a minimum spanning tree. Our algorithm runs in linear time and obtains the bestpossible tradeoff. It can be implemented on a CREW PRAM to run in logarithmic time using one processor per vertex.
Incorporating interconnect, register, and clock distribution delays into the retiming process
 IEEE Trans. on ComputerAided Design of Integrated Circuits and Systems
, 1997
"... Abstract — A retiming algorithm is presented which includes the effects of variable register, clock distribution, and interconnect delays. These delay components are incorporated into the retiming process by assigning register electrical characteristics (REC’s) to each edge in the graph representati ..."
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Cited by 18 (3 self)
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Abstract — A retiming algorithm is presented which includes the effects of variable register, clock distribution, and interconnect delays. These delay components are incorporated into the retiming process by assigning register electrical characteristics (REC’s) to each edge in the graph representation of a synchronous circuit. A matrix, called the sequential adjacency matrix (SAM), is presented that contains all path delays. Timing constraints for each data path are derived from this matrix. Vertex lags are assigned ranges rather than single values as in existing retiming algorithms. The approach used in the proposed algorithm is to initialize these ranges with unbounded values and to continuously tighten these ranges using localized timing constraints until an optimal solution is obtained. A branch and bound method is offered for the general retiming problem where the REC values are arbitrary. Certain monotonicity constraints can be placed on the REC values to permit the use of standard linear programming methods, thereby requiring significantly less computational time. These conditions and the feasibility of their application to practical circuits are presented. The algorithm is demonstrated on modified benchmark circuits and both increased clock frequencies and the elimination of all race conditions are observed. Index Terms — Clock distribution networks, clock scheduling, clock skew, clocking, interconnect delay, retiming. I.
Delay bounded buffered tree construction for timingdriven floorplanning
 PROC. IEEE INT. CONF. COMPUTER DESIGN
, 1997
"... As devices and lines shrink into the deep submicron range, the propagation delay of signals can be effectively improved by repowering the signals using intermediate buffers placed within the routing trees. Almost no existing timing driven oorplanning and placement approaches consider the option of b ..."
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Cited by 13 (0 self)
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As devices and lines shrink into the deep submicron range, the propagation delay of signals can be effectively improved by repowering the signals using intermediate buffers placed within the routing trees. Almost no existing timing driven oorplanning and placement approaches consider the option of buffer insertion. As such, they may exclude solutions, particularly early in the design process, with smaller overall area and better routability. In this paper, we propose a new methodology in which buffered trees are used to estimate wire delay during floorplanning. Instead of treating delay as one of the objectives, as done by the majority of previous work, we formulate the problem in terms of Delay Bounded Buffered Trees (DBBtree) and propose an efficient algorithm to construct a DBB spanning tree for use during floorplanning. Experimental results show that the algorithm is very effective. Using buffer insertion at the floorplanning stage yields significantly better solutions in terms of both chip area and total wire length.
Computing A DiameterConstrained Minimum Spanning Tree
, 2001
"... In numerous practical applications, it is necessary to find the smallest possible tree with a bounded diameter. A diameterconstrained minimum spanning tree (DCMST) of a given undirected, edgeweighted graph, G, is the smallestweight spanning tree of all spanning trees of G which contain no path wi ..."
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Cited by 8 (0 self)
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In numerous practical applications, it is necessary to find the smallest possible tree with a bounded diameter. A diameterconstrained minimum spanning tree (DCMST) of a given undirected, edgeweighted graph, G, is the smallestweight spanning tree of all spanning trees of G which contain no path with more than k edges, where k is a given positive integer. The problem of finding a DCMST is NPcomplete for all values of k; 4 k (n  2), except when all edgeweights are identical. A DCMST is essential for the efficiency of various distributed mutual exclusion algorithms, where it can minimize the number of messages communicated among processors per critical section. It is also useful in linear lightwave networks, where it can minimize interference in the network by limiting the traffic in the network lines. Another practical application requiring a DCMST arises in data compression, where some algorithms compress a file utilizing a tree datastructure, and decompress a path in the tree to access a record. A DCMST helps such algorithms to be fast without sacrificing a lot of storage space. We present a survey of the literature on the DCMST problem, study the expected diameter of a random labeled tree, and present five new polynomialtime algorithms for an approximate DCMST. One of our new algorithms constructs an approximate DCMST in a modified greedy fashion, employing a heuristic for selecting an edge to be added to iii the tree in each stage of the construction. Three other new algorithms start with an unconstrained minimum spanning tree, and iteratively refine it into an approximate DCMST. We also present an algorithm designed for the special case when the diameter is required to be no more than 4. Such a diameter4 tree is also used for evaluating the quality of o...
LowLight Trees, and Tight Lower Bounds for Euclidean Spanners
"... We show that for every npoint metric space M and positive integer k, there exists a spanning tree T with unweighted diameter O(k) and weight w(T) = O(k · n 1/k) · w(MST(M)), and a spanning tree T ′ with weight w(T ′ ) = O(k) · w(MST(M)) and unweighted diameter O(k · n 1/k). These trees also ach ..."
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Cited by 7 (7 self)
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We show that for every npoint metric space M and positive integer k, there exists a spanning tree T with unweighted diameter O(k) and weight w(T) = O(k · n 1/k) · w(MST(M)), and a spanning tree T ′ with weight w(T ′ ) = O(k) · w(MST(M)) and unweighted diameter O(k · n 1/k). These trees also achieve an optimal maximum degree. Furthermore, we demonstrate that these trees can be constructed efficiently. We prove that these tradeoffs between unweighted diameter and weight are tight up to constant factors in the entire range of parameters. Moreover, our lower bounds apply to a basic 1dimensional Euclidean space. Our lower bounds for the particular case of unweighted diameter O(log n) are of independent interest, settling a longstanding open problem in Computational Geometry. In STOC’95 Arya et al. devised a construction of Euclidean Spanners with unweighted diameter O(log n) and weight O(log n) · w(MST(M)). In SODA’05 Agarwal et al. showed that this result is tight up to a factor of O(log log n). We close this gap and show that the result of Arya et al. is tight up to constant factors. Finally, our upper bounds imply improved approximation algorithms for the minimum hhop spanning
Steiner ShallowLight Trees are Exponentially Lighter than Spanning Ones
"... Abstract — For a pair of parameters α, β ≥ 1, a spanning tree T of a weighted undirected nvertex graph G =(V,E,w) is called an (α, β)shallowlight tree (shortly, (α, β)SLT) of G with respect to a designated vertex rt ∈ V if (1) it approximates all distances from rt to the other vertices up to a f ..."
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Cited by 1 (0 self)
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Abstract — For a pair of parameters α, β ≥ 1, a spanning tree T of a weighted undirected nvertex graph G =(V,E,w) is called an (α, β)shallowlight tree (shortly, (α, β)SLT) of G with respect to a designated vertex rt ∈ V if (1) it approximates all distances from rt to the other vertices up to a factor of α, and (2) its weight is at most β times the weight of the minimum spanning tree MST(G) of G. The parameter α (respectively, β) is called the rootdistortion (resp., lightness) ofthetreeT. Shallowlight trees (SLTs) constitute a fundamental graph structure, with numerous theoretical and practical applications. In particular, they were used for constructing spanners, in network design, for VLSIcircuit design, for various data gathering and dissemination tasks in wireless and sensor networks, in overlay networks, and in the messagepassing model of distributed computing. Tight tradeoffs between the parameters of SLTs were established by Awerbuch et al. [5], [6] and Khuller et al. [33]. They showed that for any ɛ>0 there always exist (1 + ɛ, O ( 1))SLTs, and that ɛ the upper bound β = O ( 1) on the lightness of SLTs cannot be ɛ improved. In this paper we show that using Steiner points one can build SLTs with logarithmic lightness, i.e., β = O(log 1 ɛ).This establishes an exponential separation between spanning SLTs and Steiner ones. One particularly remarkable point on our tradeoff curve is ɛ = 0. In this regime our construction provides a shortestpath tree with weight at most O(log n) · w(MST(G)). Moreover, we prove matching lower bounds that show that all our results are tight up to constant factors. Finally, on our way to these results we settle (up to constant factors) a number of open questions that were raised by Khuller et al. [33] in SODA’93. Keywordsminimum spanning tree; shortestpath tree; Steiner