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Boolean analysis of MOS circuits
 IEEE Transactions on Computeraided Design
, 1987
"... The switchlevel model represents a digital metaloxide semiconductor (MOS) circuit as a network of charge storage nodes connected by resistive transistor switches. The functionality of such a network can be expressed as a series of systems of Boolean equations. Solving these equations symbolically ..."
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Cited by 63 (14 self)
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The switchlevel model represents a digital metaloxide semiconductor (MOS) circuit as a network of charge storage nodes connected by resistive transistor switches. The functionality of such a network can be expressed as a series of systems of Boolean equations. Solving these equations symbolically yields a set of Boolean formulas that describe the mapping from input and current state to the new network state. This analysis supports the same class of networks as the switchlevel simulator MOSSIM II and provides the same functionality, including the handling of bidirectional e ects and indeterminate (X) logic values. In the worst case, the analysis of an n node network can yield a set of formulas containing a total of O(n 3) operations. However, all but a limited set of dense, passtransistor networks give formulas with O(n) total operations. The analysis can serve as the basis of e cient programs for a variety oflogic design tasks, including: logic simulation (on both conventional and special purpose computers), fault simulation, test generation, and symbolic veri cation.
COSMOS: A compiled simulator for MOS circuits
 PROCEEDINGS OF THE 24TH DESIGN AUTOMATION CONFERENCE
, 1987
"... The cosmos simulator provides fast and accurate switchlevel modeling of mos digital circuits. It attains high performance by preprocessing the transistor network into a functionally equivalent Boolean representation. This description, produced by the symbolic analyzer anamos, captures all aspects o ..."
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Cited by 52 (0 self)
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The cosmos simulator provides fast and accurate switchlevel modeling of mos digital circuits. It attains high performance by preprocessing the transistor network into a functionally equivalent Boolean representation. This description, produced by the symbolic analyzer anamos, captures all aspects of switchlevel networks including bidirectional transistors, stored charge, different signal strengths, and indeterminate (X) logic values. The lgcc program translates the Boolean representation into a set of machine language evaluation procedures and initialized data structures. These procedures and data structures are compiled along with code implementing the simulation kernel and user interface to produce the simulation program. The simulation program runs an order of magnitude faster than our previous simulator mossim ii.
The Elmore Delay as a Bound for RC Trees with Generalized Input Signals
 the IEEE Transactions on CAD. (Available
"... The Elmore delay is an extremely popular delay metric, particularly for RC tree analysis. The widespread usage of this metric is mainly attributable to it being the most accurate delay measure that is a simple analytical function of the circuit parameters. The only drawbacks to this delay metric are ..."
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Cited by 38 (0 self)
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The Elmore delay is an extremely popular delay metric, particularly for RC tree analysis. The widespread usage of this metric is mainly attributable to it being the most accurate delay measure that is a simple analytical function of the circuit parameters. The only drawbacks to this delay metric are the uncertainty as to whether it is an optimistic or a pessimistic estimate, and the restriction to step response delay estimation. In this paper, we prove that the Elmore delay is an absolute upper bound on the 50 % delay of an RC tree response. Moreover, we prove that this bound holds for input signals other than steps, and that the actual delay asymptotically approaches the Elmore delay as the input signal rise time increases. A lower bound on the delay is also developed using the Elmore delay and the second moment of the impulse response. The utility of this bound is for understanding the accuracy and the limitations of the Elmore delay metric as we use it for design automation. I.
Computing signal delay in general RC networks by tree/link partitioning
 IEEE Transactions on ComputerAided Design
, 1990
"... S. Patel and J. Patel, “Effectiveness of heuristics for automatic test ..."
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Cited by 29 (0 self)
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S. Patel and J. Patel, “Effectiveness of heuristics for automatic test
Algorithmic Aspects of Symbolic Switch Network Analysis
 IEEE Trans. CAD/IC
, 1987
"... A network of switches controlled by Boolean variables can be represented as a system of Boolean equations. The solution of this system gives a symbolic description of the conducting paths in the network. Gaussian elimination provides an efficient technique for solving sparse systems of Boolean eq ..."
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Cited by 16 (5 self)
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A network of switches controlled by Boolean variables can be represented as a system of Boolean equations. The solution of this system gives a symbolic description of the conducting paths in the network. Gaussian elimination provides an efficient technique for solving sparse systems of Boolean equations. For the class of networks that arise when analyzing digital metaloxide semiconductor (MOS) circuits, a simple pivot selection rule guarantees that most s switch networks encountered in practice can be solved with O(s) operations. When represented by a directed acyclic graph, the set of Boolean formulas generated by the analysis has total size bounded by the number of operations required by the Gaussian elimination. This paper presents the mathematical basis for systems of Boolean equations, their solution by Gaussian elimination, and data structures and algorithms for representing and manipulating Boolean formulas.
Symbolic Verification of MOS Circuits
, 1985
"... The program MOSSYM simulates the behavior of a MOS circuit represented as a switchlevel network symbolically. That is, during simulator operation the user can set an input to either 0, 1, or a Boolean variable. The simulator then computes the behavior of the circuit as a function of the past and pr ..."
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Cited by 13 (6 self)
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The program MOSSYM simulates the behavior of a MOS circuit represented as a switchlevel network symbolically. That is, during simulator operation the user can set an input to either 0, 1, or a Boolean variable. The simulator then computes the behavior of the circuit as a function of the past and present input variables. By using heuristically efficient Boolean function manipulation algorithms, the verification of a circuit by symbolic simulation can proceed much more quickly than by exhaustive logic simulation. In this paper we present our concept of symbolic simulation, derive an algorithm for switchlevel symbolic simulation, and present experimental measurements from MOSSYM.
Analysis of Power Supply Networks in VLSI Circuits
, 1991
"... Although the trend toward finer geometries and larger chips has produced faster systems, it has also created larger voltage drops and higher current densities in chip power supply networks. Excessive voltage drops in the power supply lines cause incorrect circuit operation, and high current densitie ..."
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Cited by 5 (2 self)
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Although the trend toward finer geometries and larger chips has produced faster systems, it has also created larger voltage drops and higher current densities in chip power supply networks. Excessive voltage drops in the power supply lines cause incorrect circuit operation, and high current densities lead to circuit failure via electromigration. Analyzing this power supply noise by hand for large circuits is difficult and error prone; automatic checking tools are needed to make the analysis easier. This thesis describes Ariel, a CAD tool that helps VLSI designers analyze power supply noise. The system consists of three main components, a resistance extractor, a current estimator, and a linear solver, that are used together to determine the voltage drops and current density along the supply lines. The resistance extractor includes two parts: a fast extractor that calculates resistances quickly using simple heuristics, and a slower, more accurate finite element extractor. Despite its simplicity, the fast extractor obtained nearly the same results as the finite element one and is two orders of magnitude faster. The system also contains two current estimators, one for CMOS
Architectural Synthesis via VHDL
, 1991
"... In this paper, we present results from our experiments integrating an architectural synthesis tool, SandS, into the Keystone VLSI design environment. The resulting Architectural VHDL Synthesis tool is called TinkerTool. It provides a means by which a designer can conceive and configure complex desig ..."
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Cited by 1 (1 self)
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In this paper, we present results from our experiments integrating an architectural synthesis tool, SandS, into the Keystone VLSI design environment. The resulting Architectural VHDL Synthesis tool is called TinkerTool. It provides a means by which a designer can conceive and configure complex designs in a high level behavioral language to automatically generate hierarchical VHDL. The tool allows designers to take a "black box" approach to design, so that they do not need to know the implementation details of components or subcomponents below the current one. Consequently, both top down and bottom up design methodologies can be used. Similarly, any circuit design modeled in VHDL can be ported into the component library to be used in the next level of hierarchical design. A major impact of this hierarchical component approach is that representations, other than VHDL, can be attached to a component and one could construct the entire design along a particular implementation path. For ex...
Piecewise Linear Models for Rsim
, 1993
"... Rsim is a switchlevel simulator which can simulate large digital MOS integrated circuits with speedups of over 3 orders of magnitude over SPICE. Unfortunately, Rsim's simple switchedresistor model renders it incapable of simulating certain CMOS and most BiCMOS and ECL digital circuits. We obser ..."
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Cited by 1 (0 self)
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Rsim is a switchlevel simulator which can simulate large digital MOS integrated circuits with speedups of over 3 orders of magnitude over SPICE. Unfortunately, Rsim's simple switchedresistor model renders it incapable of simulating certain CMOS and most BiCMOS and ECL digital circuits. We observe that the switchedresistor model is just one particular piecewise linear model and that Rsim's simulation framework can accommodate more elaborate piecewise linear models. The resulting simulator, Mom, combines the efficiency of switchlevel simulation with the ability to simulate a wider variety of circuits. We demonstrate Mom's efficiency and flexibility on a variety of circuits. This research was supported in part by DARPA contract N0003991C1038. d i g i t a l Western Research Laboratory 250 University Avenue Palo Alto, California 94301 USA 1 Introduction The high cost of semiconductor processing makes it desirable to verify the correctness of a large custom digital integr...