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62
Survey of Sticking Effects for Micro Parts Handling
, 1995
"... When parts to be handled are less than one millimeter in size, adhesive forces between gripper and object can be significant compared to gravitational forces. These adhesive forces arise primarily from surface tension, Van der Waals, and electrostatic attractions and can be a fundamental limitation ..."
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Cited by 52 (3 self)
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When parts to be handled are less than one millimeter in size, adhesive forces between gripper and object can be significant compared to gravitational forces. These adhesive forces arise primarily from surface tension, Van der Waals, and electrostatic attractions and can be a fundamental limitation to part handling in a gas environment. While it is possible to fabricate miniature versions of conventional robot grippers, for example from polysilicon, it appears that it will be difficult to overcome adhesion effects for the smallest parts. Thus, manipulation of parts on the order of 10 micron or smaller may best be done in a fluid medium using techniques such as laser trapping, or dielectrophoresis. 1 Adhesion Forces A typical robotic manipulation scenario is the sequence of operations pick, transport, and place. For parts with masses of several grams, the gravitational force will usually dominate adhesive forces, and parts will drop when the gripper opens. For parts with size less tha...
Design of highspeed, lowpower frequency dividers and phaselocked loops in deep submicron CMOS
 IEEE J. SolidState Circuits
, 1995
"... Abstract—Deep submicron CMOS technologies offer the high speed and low power dissipation required in multigigahertz communication systems such as optical data links and wireless products. This paper introduces the design of two communication circuits, namely a 1/2 frequency divider and a phaselocke ..."
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Cited by 21 (2 self)
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Abstract—Deep submicron CMOS technologies offer the high speed and low power dissipation required in multigigahertz communication systems such as optical data links and wireless products. This paper introduces the design of two communication circuits, namely a 1/2 frequency divider and a phaselocked loop, fabricated in a partially scaled 0.1 "m CMOS technology. Configured as a masterslave circuit, the divider achieves a maximum speed of 13.4 GHz with a power dissipation of 28 mW. The phaselocked loop employs a currentcontrolled oscillator and a symmetric mixer to operate at 3 GHz with a tracking range of 6320 MHz, an rms jitter of 2.5 ps, and a phase noise of 0100 dBc/Hz while dissipating 25 mW. I.
Elementary Scattering Theory of the Si MOSFET
 IEEE Electron Device Lett
, 1997
"... A oneflux scattering theory of the silicon MOSFET is introduced. The result gives the currentvoltage characteristic in terms of scattering parameters rather than a mobility. For long channel transistors, the results reduce to conventional driftdiffusion theory, but they also apply to devices in w ..."
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Cited by 15 (2 self)
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A oneflux scattering theory of the silicon MOSFET is introduced. The result gives the currentvoltage characteristic in terms of scattering parameters rather than a mobility. For long channel transistors, the results reduce to conventional driftdiffusion theory, but they also apply to devices in which the channel length is comparable to or even shorter than the meanfreepath. The results indicate that for very short channels the transconductance will be limited by carrier injection at the source and that velocity overshoot is not the controlling factor. The theory also indicates that evaluation of the drain current in short channel MOSFETs is really a nearequilibrium problem, even though the channel electric field is large in magnitude and varies rapidly in space.
Electronics Below 10 nm
 In Nano and Giga Challenges in Microelectronics
, 2003
"... This chapter reviews prospects for the development and practical introduction of ultrasmall electron devices, including nanoscale fieldeffect transistors (FETs) and singleelectron transistors (SETs), as well as new concepts for nanometerscalable memory cells. Physics allows silicon FETs to be sca ..."
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Cited by 9 (4 self)
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This chapter reviews prospects for the development and practical introduction of ultrasmall electron devices, including nanoscale fieldeffect transistors (FETs) and singleelectron transistors (SETs), as well as new concepts for nanometerscalable memory cells. Physics allows silicon FETs to be scaled down to ∼3 nm gate length, but below ∼10 nm the devices are extremely sensitive to minute (subnanometer) fabrication spreads. This sensitivity may send the fabrication facilities costs (high even now) skyrocketing, and lead to the end of the Moore Law some time during the next decade. Lithographically defined SETs can hardly be a panacea, since the critical dimension of such transistor (its singleelectron island size) for the room temperature operation should be below ∼1 nm. Apparently, the only breakthrough that would allow to make 1nmscale electron devices practical, would be the introduction of “CMOL ” hybrid integrated circuits that would feature, in addition to an advanced CMOS subsystem, a layer of ultradense molecular electron devices. These devices would be fabricated by chemicallyassisted selfassembly from solution on fewnmpitch nanowire arrays connecting them to the CMOS stack. Due to the finite yield of molecular devices and their sensitivity to random charged impurities, this approach will require a substantial revision of integrated circuit architectures, ranging from defecttolerant versions of memory matrices and number crunching processors to more radical solutions like hardwareimplemented neuromorphic networks capable of advanced image recognition and more intelligent information processing tasks.
VoltageCurrent Characteristics of MultiDimensional Semiconductor Devices
 Quarterly of Appl. Math
, 1991
"... The steady state driftdiffusion model for the flow of electrons and holes in semiconductors is simplified by perturbation techniques. The simplifications amount to assuming zero space charge and low injection. The limiting problems are solved and explicit formulas for the voltagecurrent characteri ..."
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Cited by 4 (2 self)
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The steady state driftdiffusion model for the flow of electrons and holes in semiconductors is simplified by perturbation techniques. The simplifications amount to assuming zero space charge and low injection. The limiting problems are solved and explicit formulas for the voltagecurrent characteristics of bipolar devices can be obtained. As examples, the pndiode, the bipolar transistor and the thyristor are discussed. While the classical results of a onedimensional analysis are confirmed in the case of the diode, some important effects of the higher dimensionality appear for the bipolar transistor. 1. Introduction The classical driftdiffusion model for the steady flow of negatively charged electrons (density n(x)) and positively charged holes (density p(x)) in a semiconductor consists of the continuity equations div Jn = \Gammadiv J p = R; (1:1a) the current relations ffi 4 Jn = ¯n (rn \Gamma nrV ); ffi 4 J p = \Gamma¯ p (rp + prV ); (1:1b) and the Poisson equation 2 \D...
Diffusion limit of a semiconductor BoltzmannPoisson system
 SIAM J. Math. Anal
"... Abstract. The paper deals with the diffusion limit of the initialboundary value problem for the multidimensional semiconductor BoltzmannPoisson system. Here, we generalize the one dimensional results obtained in [6] to the case of several dimensions using global renormalized solutions. The method ..."
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Cited by 4 (2 self)
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Abstract. The paper deals with the diffusion limit of the initialboundary value problem for the multidimensional semiconductor BoltzmannPoisson system. Here, we generalize the one dimensional results obtained in [6] to the case of several dimensions using global renormalized solutions. The method of moments and a velocity averaging lemma are used to prove the convergence of the renormalized solutions to the semiconductor BoltzmannPoisson system towards a global weak solution of the DriftDiffusionPoisson model. Key words. Kinetic transport equations, semiconductor BoltzmannPoisson system, DriftDiffusion model, Entropy dissipation, moment method, velocity averaging lemma, renormalized solution,... 1 1 Introduction and Main results In this paper, we study the diffusion limit of the initialboundary value problem for the semiconductor BoltzmannPoisson system (see [27, 31]). The model we consider here is associated with a linear low density approximation of the electronphonon collisions. In other words it is a low density approximation of the physically correct
QuantumConfined Stark Effect in Ge/SiGe Quantum Wells on Si for Optical Modulators
 IEEE Journal of Selected Topics in Quantum Electronics
"... Abstract—We present observations of quantum confinement and quantumconfined Stark effect (QCSE) electroabsorption in Ge quantum wells with SiGe barriers grown on Si substrates, in good agreement with theoretical calculations. Though Ge is an indirect gap semiconductor, the resulting effects are at ..."
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Cited by 4 (0 self)
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Abstract—We present observations of quantum confinement and quantumconfined Stark effect (QCSE) electroabsorption in Ge quantum wells with SiGe barriers grown on Si substrates, in good agreement with theoretical calculations. Though Ge is an indirect gap semiconductor, the resulting effects are at least as clear and strong as seen in typical III–V quantum well structures at similar wavelengths. We also demonstrate that the effect can be seen over the Cband around 1.55µm wavelength in structures heated to 90 ◦C, similar to the operating temperature of silicon electronic chips. The physics of the effects are discussed, including the effects of strain, electron and hole confinement, and exciton binding, and the reasons why the effects should be observable at all in such an indirect gap material. This effect is very promising for practical highspeed, lowpower optical modulators fabricated compatible with mainstream silicon electronic integrated circuits. Index Terms—Electroabsorption effect, germanium, optical interconnections, optical modulators, quantumconfined Stark effect (QCSE), silicon. I.
InAs/InP radial nanowire heterostructures as high electron mobility devices
 Nano Lett
"... Radial core/shell nanowires (NWs) represent an important class of onedimensional (1D) systems with substantial potential for exploring fundamental materials electronic and photonic properties. Here, we report the rational design and synthesis of InAs/InP core/shell NW heterostructures with quantum ..."
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Cited by 3 (0 self)
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Radial core/shell nanowires (NWs) represent an important class of onedimensional (1D) systems with substantial potential for exploring fundamental materials electronic and photonic properties. Here, we report the rational design and synthesis of InAs/InP core/shell NW heterostructures with quantumconfined, highmobility electron carriers. Transmission electron microscopy studies revealed singlecrystal InAs cores with epitaxial InP shells 2−3 nm in thickness, and energydispersive Xray spectroscopy analysis further confirmed the composition of the designed heterostructure. Roomtemperature electrical measurements on InAs/InP NW fieldeffect transistors (NWFETs) showed significant improvement in the oncurrent and transconductance compared to InAs NWFETs fabricated in parallel, with a roomtemperature electron mobility, 11 500 cm 2 /Vs, substantially higher than other synthesized 1D nanostructures. In addition, NWFET devices configured with integral high dielectric constant gate oxide and topgate structure yielded scaled oncurrents up to 3.2 mA/µm, which are larger than values reported for other nchannel FETs. The design and realization of high electron mobility InAs/InP NWs extends our toolbox of nanoscale building blocks and opens up opportunities for fundamental and applied studies of quantum coherent transport and highspeed, lowpower nanoelectronic circuits. Central to the “bottomup ” vision for nanoscale science and technology is the design and rational synthesis of building blocks with welldefined physical properties. 1 Semiconductor
Article Measurement of Blood Pressure Using an Arterial Pulsimeter Equipped with a Hall Device
, 2011
"... sensors ..."
Sub100 nanometer channel length Ge/Si nanowire transistors with potential for 2 THz switching speed
 Nano Lett
, 2008
"... Ge/Si core/shell nanowires (NWs) are attractive and flexible building blocks for nanoelectronics ranging from fieldeffect transistors (FETs) to lowtemperature quantum devices. Here we report the first studies of the sizedependent performance limits of Ge/Si NWFETs in the sub100 nm channel length ..."
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Cited by 2 (0 self)
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Ge/Si core/shell nanowires (NWs) are attractive and flexible building blocks for nanoelectronics ranging from fieldeffect transistors (FETs) to lowtemperature quantum devices. Here we report the first studies of the sizedependent performance limits of Ge/Si NWFETs in the sub100 nm channel length regime. Metallic nanoscale electrical contacts were made and used to define sub100 nm Ge/Si channels by controlled solidstate conversion of Ge/Si NWs to NiSixGey alloys. Electrical transport measurements and modeling studies demonstrate that the nanoscale metallic contacts overcome deleterious shortchannel effects present in lithographically defined sub100 nm channels. Data acquired on 70 and 40 nm channel length Ge/Si NWFETs with a drainsource bias of 0.5 V yield transconductance values of 78 and 91 µS, respectively, and maximum oncurrents of 121 and 152 µA. The scaled transconductance and oncurrent values for a gate and bias voltage window of 0.5 V were 6.2 mS/µm and 2.1 mA/µm, respectively, for the 40 nm device and exceed the best reported values for planar Si and NW ptype FETs. In addition, analysis of the intrinsic switching delay shows that terahertz intrinsic operation speed is possible when channel length is reduced to 70 nm and that an intrinsic delay of 0.5 ps is achievable in our 40 nm device. Comparison of the experimental data with simulations based on a semiclassical, ballistic transport model suggests that these sub100 nm Ge/Si NWFETs with integrated highK gate dielectric operate near the ballistic limit. There exist a growing number of challenges1 associated with continuation of the remarkable scaling in performance and density of planar FETs achieved in the semiconductor industry over the past several decades due to physical and technical limitations of current device structures. 2,3