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16
A Framework for Dynamic Graph Drawing
 CONGRESSUS NUMERANTIUM
, 1992
"... Drawing graphs is an important problem that combines flavors of computational geometry and graph theory. Applications can be found in a variety of areas including circuit layout, network management, software engineering, and graphics. The main contributions of this paper can be summarized as follows ..."
Abstract

Cited by 544 (40 self)
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Drawing graphs is an important problem that combines flavors of computational geometry and graph theory. Applications can be found in a variety of areas including circuit layout, network management, software engineering, and graphics. The main contributions of this paper can be summarized as follows: ffl We devise a model for dynamic graph algorithms, based on performing queries and updates on an implicit representation of the drawing, and we show its applications. ffl We present several efficient dynamic drawing algorithms for trees, seriesparallel digraphs, planar stdigraphs, and planar graphs. These algorithms adopt a variety of representations (e.g., straightline, polyline, visibility), and update the drawing in a smooth way.
Parallel transitive closure and point location in planar structures
 SIAM J. COMPUT
, 1991
"... Parallel algorithms for several graph and geometric problems are presented, including transitive closure and topological sorting in planar stgraphs, preprocessing planar subdivisions for point location queries, and construction of visibility representations and drawings of planar graphs. Most of th ..."
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Cited by 24 (12 self)
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Parallel algorithms for several graph and geometric problems are presented, including transitive closure and topological sorting in planar stgraphs, preprocessing planar subdivisions for point location queries, and construction of visibility representations and drawings of planar graphs. Most of these algorithms achieve optimal O(log n) running time using n = log n processors in the EREW PRAM model, n being the number of vertices.
Fast floorplanning by lookahead enabled recursive bipartitioning
 In Asia South Pacific Design Automation Conf
, 2005
"... A new paradigm is introduced for floorplanning any combination of fixedshape and variableshape blocks under tight fixedoutline area constraints and a wirelength objective. Dramatic improvement over traditional floorplanning methods is achieved by explicit construction of strictly legal layouts fo ..."
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Cited by 22 (2 self)
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A new paradigm is introduced for floorplanning any combination of fixedshape and variableshape blocks under tight fixedoutline area constraints and a wirelength objective. Dramatic improvement over traditional floorplanning methods is achieved by explicit construction of strictly legal layouts for every partition block at every level of a cutsizedriven, topdown hierarchy. By scalably incorporating legalization into the hierarchical flow, posthoc legalization is successfully eliminated. For large floorplanning benchmarks, an implementation, called PATOMA, generates solutions with half the wirelength of stateoftheart floorplanners in orders of magnitude less run time. Experiments on standard GSRC industry benchmarks compare an implementation, called PATOMA, to the Traffic floorplanner and to both the default and higheffort modes of the Parquet2 floorplanner. With all blocks hard, PATOMA’s average wirelength is 38 % shorter than Traffic’s in the same run time. With all blocks soft, PATOMA on average produces wirelengths 16 % shorter than Parquet2’s default mode and runs 37 ¢ faster. Compared to the higheffort mode of Parquet2, PATOMA’s average wirelength is 8 % shorter, and it runs 824 ¢ faster, on average. I.
Computing Cartograms with Optimal Complexity
"... In a rectilinear dual of a planar graph vertices are represented by simple rectilinear polygons and edges are represented by sidecontact between the corresponding polygons. A rectilinear dual is called a cartogram if the area of each region is equal to a prespecified weight of the corresponding ve ..."
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Cited by 9 (8 self)
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In a rectilinear dual of a planar graph vertices are represented by simple rectilinear polygons and edges are represented by sidecontact between the corresponding polygons. A rectilinear dual is called a cartogram if the area of each region is equal to a prespecified weight of the corresponding vertex. The complexity of a cartogram is determined by the maximum number of corners (or sides) required for any polygon. In a series of papers the polygonal complexity of such representations for maximal planar graphs has been reduced from the initial 40 to 34, then to 12 and very recently to the currently best known 10. Here we describe a construction with 8sided polygons, which is optimal in terms of polygonal complexity as 8sided polygons are sometimes necessary. Specifically, we show how to compute the combinatorial structure and how to refine the representation into an areauniversal rectangular layout in linear time. The exact cartogram can be computed from the areauniversal rectangular layout with numerical iteration, or can be approximated with a hillclimbing heuristic. We also describe an alternative construction for Hamiltonian maximal planar graphs, which allows us to directly compute the cartograms in linear time. Moreover, we prove that even for Hamiltonian graphs 8sided rectilinear polygons are necessary, by constructing a nontrivial lower bound example. The complexity of the cartograms can be reduced to 6 if the Hamiltonian path has the extra property that it is onelegged, as in outerplanar graphs. Thus, we have optimal representations (in terms of both polygonal complexity and running time) for Hamiltonian maximal planar and maximal outerplanar graphs.
A Framework for the Static and Interactive Visualization of Statecharts
, 2002
"... We present a framework for the automatic generation of layouts of statechart diagrams. Statecharts [16] are widely used for the requirements specification of reactive systems. Our framework is based on several techniques that include hierarchical drawing, labeling, and floorplanning, designed to ..."
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Cited by 8 (0 self)
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We present a framework for the automatic generation of layouts of statechart diagrams. Statecharts [16] are widely used for the requirements specification of reactive systems. Our framework is based on several techniques that include hierarchical drawing, labeling, and floorplanning, designed to work in a cooperative environment. Therefore, the resulting drawings enjoy several important properties: they emphasize the natural hierarchical decomposition of states into substates; they have a low number of edge crossings; they have good aspect ratio; and require a small area. We also present techniques for interactive operations. We have implemented our framework and obtained drawings for several statechart examples.
On a visibility representation of graphs
 IN [41
, 1996
"... We give a visibility representation of graphs which extends some very wellknown representations considered extensively in the literature. Concretely, the vertices are represented by a collection of parallel hyperrectangles in R n and the visibility is orthogonal to those hyperrectangles. With thi ..."
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Cited by 6 (0 self)
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We give a visibility representation of graphs which extends some very wellknown representations considered extensively in the literature. Concretely, the vertices are represented by a collection of parallel hyperrectangles in R n and the visibility is orthogonal to those hyperrectangles. With this generalization, we can prove that each graph admits a visibility representation. But, it arises the problem of determining the minimum Euclidean space where such representation is possible. We consider this problem for concrete wellknown families of graphs such as planar graphs, complete graphs and complete bipartite graphs.
personal communication
 in Tokyo, Japan in 1969. Herb0q/ ed the B.E., M.E., and Ph.D.degrb0 inelectrbCH engineerGH fre Keio Univervb y in 1992, 1994 and 1997,r97 ectively. Fr7
, 1995
"... We prove a conjecture of Ackerman, Barequet and Pinter. Every floorplan with n internal segments can be embedded on every set of n points in generic position. The construction makes use of area universal floorplans also known as area universal rectangular layouts. The notion of area used in our con ..."
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Cited by 2 (0 self)
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We prove a conjecture of Ackerman, Barequet and Pinter. Every floorplan with n internal segments can be embedded on every set of n points in generic position. The construction makes use of area universal floorplans also known as area universal rectangular layouts. The notion of area used in our context depends on a nonuniform density function. We, therefore, have to generalize the theory of area universal floorplans to this situation. For the proof we use the airpressure approach of Izumi, Takahashi and Kajitani. The method is then used to prove a result about accommodating points in floorplans that is slightly more general than the original conjecture. We close with some remarks on the counting problem that motivated the conjecture of Ackerman et al.
Intel Corporation
"... The problem of optimal space allocation among interconnect wires in a VLSI layout, in order to minimize the switching power consumption and the average signal delay, is addressed in this article. We define a Weighted PowerDelay Sum (WPDS) objective function and derive necessary and sufficient condi ..."
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The problem of optimal space allocation among interconnect wires in a VLSI layout, in order to minimize the switching power consumption and the average signal delay, is addressed in this article. We define a Weighted PowerDelay Sum (WPDS) objective function and derive necessary and sufficient conditions for the existence of optimal interwire space allocation, based on the notion of capacitance density. At the optimum, every wire must be in equilibrium of its linetoline weighted capacitance density on its two opposite sides, and the WPDS of the whole circuit is minimal if and only if capacitance density is uniformly distributed across the entire layout. This condition is shown to be equivalent to all paths of the layout crosscapacitance graph having the same length and all cuts having the same flow. An implementation which has been used in the design of a recent commercial highend microprocessor and yielded 17 % power reduction and 9 % delay reduction in toplevel interconnects is presented.
. Thus (x
"... where every module uses the smallest possible xdimension permitted by its shape constraint, and let z 1 ..."
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where every module uses the smallest possible xdimension permitted by its shape constraint, and let z 1
REPRESENTATIONS OF GRAPHS ON A CYLINDER*
"... Abstract. A complete characterization ofthe class ofgraphs that admit a cylindric visibility representation is presented, where vertices are representedby intervals parallel to the axis ofthe cylinderand the edgescorrespond to pairs ofvisible intervals. Moreover, lineartime algorithms are given for ..."
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Abstract. A complete characterization ofthe class ofgraphs that admit a cylindric visibility representation is presented, where vertices are representedby intervals parallel to the axis ofthe cylinderand the edgescorrespond to pairs ofvisible intervals. Moreover, lineartime algorithms are given for testing the existence ofand constructing such a representation. Important applications ofcylindric visibility representations can be found in the layout ofregular VLSI circuits, such as linear systolic arrays and bitslice architectures. Also, alternative &quot;dual &quot; characterizations are presented ofthe graphs that admit visibility representations in the plane and in the cylinder. It is interesting to observe that neither of these two classes is contained in the other, although they have a nonempty intersection. Key words, visibility graph, visibility representation, design and analysis of algorithms, computational geometry, cylinder, planar graph, caterpillar AMS(MOS) subject classifications. 68R10, 68U05, 05C10, 05C75 1. Introduction. The