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A Framework for Dynamic Graph Drawing
 CONGRESSUS NUMERANTIUM
, 1992
"... Drawing graphs is an important problem that combines flavors of computational geometry and graph theory. Applications can be found in a variety of areas including circuit layout, network management, software engineering, and graphics. The main contributions of this paper can be summarized as follows ..."
Abstract

Cited by 520 (40 self)
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Drawing graphs is an important problem that combines flavors of computational geometry and graph theory. Applications can be found in a variety of areas including circuit layout, network management, software engineering, and graphics. The main contributions of this paper can be summarized as follows: ffl We devise a model for dynamic graph algorithms, based on performing queries and updates on an implicit representation of the drawing, and we show its applications. ffl We present several efficient dynamic drawing algorithms for trees, seriesparallel digraphs, planar stdigraphs, and planar graphs. These algorithms adopt a variety of representations (e.g., straightline, polyline, visibility), and update the drawing in a smooth way.
Parallel transitive closure and point location in planar structures
 SIAM J. COMPUT
, 1991
"... Parallel algorithms for several graph and geometric problems are presented, including transitive closure and topological sorting in planar stgraphs, preprocessing planar subdivisions for point location queries, and construction of visibility representations and drawings of planar graphs. Most of th ..."
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Cited by 23 (11 self)
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Parallel algorithms for several graph and geometric problems are presented, including transitive closure and topological sorting in planar stgraphs, preprocessing planar subdivisions for point location queries, and construction of visibility representations and drawings of planar graphs. Most of these algorithms achieve optimal O(log n) running time using n = log n processors in the EREW PRAM model, n being the number of vertices.
Fast floorplanning by lookahead enabled recursive bipartitioning
 In Asia South Pacific Design Automation Conf
, 2005
"... A new paradigm is introduced for floorplanning any combination of fixedshape and variableshape blocks under tight fixedoutline area constraints and a wirelength objective. Dramatic improvement over traditional floorplanning methods is achieved by explicit construction of strictly legal layouts fo ..."
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Cited by 22 (2 self)
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A new paradigm is introduced for floorplanning any combination of fixedshape and variableshape blocks under tight fixedoutline area constraints and a wirelength objective. Dramatic improvement over traditional floorplanning methods is achieved by explicit construction of strictly legal layouts for every partition block at every level of a cutsizedriven, topdown hierarchy. By scalably incorporating legalization into the hierarchical flow, posthoc legalization is successfully eliminated. For large floorplanning benchmarks, an implementation, called PATOMA, generates solutions with half the wirelength of stateoftheart floorplanners in orders of magnitude less run time. Experiments on standard GSRC industry benchmarks compare an implementation, called PATOMA, to the Traffic floorplanner and to both the default and higheffort modes of the Parquet2 floorplanner. With all blocks hard, PATOMA’s average wirelength is 38 % shorter than Traffic’s in the same run time. With all blocks soft, PATOMA on average produces wirelengths 16 % shorter than Parquet2’s default mode and runs 37 ¢ faster. Compared to the higheffort mode of Parquet2, PATOMA’s average wirelength is 8 % shorter, and it runs 824 ¢ faster, on average. I.
Computing Cartograms with Optimal Complexity
"... In a rectilinear dual of a planar graph vertices are represented by simple rectilinear polygons and edges are represented by sidecontact between the corresponding polygons. A rectilinear dual is called a cartogram if the area of each region is equal to a prespecified weight of the corresponding ve ..."
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Cited by 9 (7 self)
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In a rectilinear dual of a planar graph vertices are represented by simple rectilinear polygons and edges are represented by sidecontact between the corresponding polygons. A rectilinear dual is called a cartogram if the area of each region is equal to a prespecified weight of the corresponding vertex. The complexity of a cartogram is determined by the maximum number of corners (or sides) required for any polygon. In a series of papers the polygonal complexity of such representations for maximal planar graphs has been reduced from the initial 40 to 34, then to 12 and very recently to the currently best known 10. Here we describe a construction with 8sided polygons, which is optimal in terms of polygonal complexity as 8sided polygons are sometimes necessary. Specifically, we show how to compute the combinatorial structure and how to refine the representation into an areauniversal rectangular layout in linear time. The exact cartogram can be computed from the areauniversal rectangular layout with numerical iteration, or can be approximated with a hillclimbing heuristic. We also describe an alternative construction for Hamiltonian maximal planar graphs, which allows us to directly compute the cartograms in linear time. Moreover, we prove that even for Hamiltonian graphs 8sided rectilinear polygons are necessary, by constructing a nontrivial lower bound example. The complexity of the cartograms can be reduced to 6 if the Hamiltonian path has the extra property that it is onelegged, as in outerplanar graphs. Thus, we have optimal representations (in terms of both polygonal complexity and running time) for Hamiltonian maximal planar and maximal outerplanar graphs.
On a visibility representation of graphs
 IN [41
, 1996
"... We give a visibility representation of graphs which extends some very wellknown representations considered extensively in the literature. Concretely, the vertices are represented by a collection of parallel hyperrectangles in R n and the visibility is orthogonal to those hyperrectangles. With thi ..."
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Cited by 6 (0 self)
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We give a visibility representation of graphs which extends some very wellknown representations considered extensively in the literature. Concretely, the vertices are represented by a collection of parallel hyperrectangles in R n and the visibility is orthogonal to those hyperrectangles. With this generalization, we can prove that each graph admits a visibility representation. But, it arises the problem of determining the minimum Euclidean space where such representation is possible. We consider this problem for concrete wellknown families of graphs such as planar graphs, complete graphs and complete bipartite graphs.
Novel Convex Optimization Approaches for VLSI Floorplanning
"... c○Chaomin Luo 2008I hereby declare that I am the sole author of this thesis. This is a true copy of the thesis, including any required final revisions, as accepted by my examiners. I understand that my thesis may be made electronically available to the public. The floorplanning problem aims to arran ..."
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c○Chaomin Luo 2008I hereby declare that I am the sole author of this thesis. This is a true copy of the thesis, including any required final revisions, as accepted by my examiners. I understand that my thesis may be made electronically available to the public. The floorplanning problem aims to arrange a set of rectangular modules on a rectangular chip area so as to optimize an appropriate measure of performance. This problem is known to be NPhard, and is particularly challenging if the chip dimensions are fixed. Fixedoutline floorplanning is becoming increasingly important as a tool to design flows in the hierarchical design of Application Specific Integrated Circuits and SystemOnChip. Therefore, it has recently received much attention. A twostage convex optimization methodology is proposed to solve the fixedoutline floorplanning problem. It is a global optimization problem for wirelength minimization. In the first stage, an attractorrepeller convex optimization model provides the relative positions of the modules on the floorplan. The second stage places and sizes the modules using convex optimization. Given the relative positions of the
Intel Corporation
"... The problem of optimal space allocation among interconnect wires in a VLSI layout, in order to minimize the switching power consumption and the average signal delay, is addressed in this article. We define a Weighted PowerDelay Sum (WPDS) objective function and derive necessary and sufficient condi ..."
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The problem of optimal space allocation among interconnect wires in a VLSI layout, in order to minimize the switching power consumption and the average signal delay, is addressed in this article. We define a Weighted PowerDelay Sum (WPDS) objective function and derive necessary and sufficient conditions for the existence of optimal interwire space allocation, based on the notion of capacitance density. At the optimum, every wire must be in equilibrium of its linetoline weighted capacitance density on its two opposite sides, and the WPDS of the whole circuit is minimal if and only if capacitance density is uniformly distributed across the entire layout. This condition is shown to be equivalent to all paths of the layout crosscapacitance graph having the same length and all cuts having the same flow. An implementation which has been used in the design of a recent commercial highend microprocessor and yielded 17 % power reduction and 9 % delay reduction in toplevel interconnects is presented.
Proportional Contact Representations of 4connected Planar Graphs
"... Abstract. In a contact representation of a planar graph, vertices are represented by interiordisjoint polygons and two polygons share a nonempty common boundary when the corresponding vertices are adjacent. In the weighted version, a weight is assigned to each vertex and a contact representation i ..."
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Abstract. In a contact representation of a planar graph, vertices are represented by interiordisjoint polygons and two polygons share a nonempty common boundary when the corresponding vertices are adjacent. In the weighted version, a weight is assigned to each vertex and a contact representation is called proportional if each polygon realizes an area proportional to the vertex weight. In this paper we study proportional contact representations of 4connected internally triangulated planar graphs. The best known lower and upper bounds on the polygonal complexity for such graphs are 4 and 8, respectively. We narrow the gap between them by proving the existence of a representation with complexity 6. We then disprove a 10year old conjecture on the existence of a Hamiltonian canonical cycle in a 4connected maximal planar graph, which also implies that a previously suggested method for constructing proportional contact representations of complexity 6 for these graphs will not work. Finally we prove that it is NPcomplete to decide whether a 4connected planar graph admits a contact representation using only rectangles. 1
Exploiting AirPressure to Map Floorplans on Point Sets
"... Abstract. We prove a conjecture of Ackerman, Barequet and Pinter. Every floorplan with n segments can be embedded on every set of n points in generic position. The construction makes use of area universal floorplans also known as area universal rectangular layouts. The notion of area used in our con ..."
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Abstract. We prove a conjecture of Ackerman, Barequet and Pinter. Every floorplan with n segments can be embedded on every set of n points in generic position. The construction makes use of area universal floorplans also known as area universal rectangular layouts. The notion of area used in our context depends on a nonuniform density function. We, therefore, have to generalize the theory of area universal floorplans to this situation. The method is then used to prove a result about accommodating points in floorplans that is slightly more general than the conjecture of Ackerman et al.
AT&T Labs and
"... Contact graphs of isothetic rectangles unify many concepts from applications including VLSI and architectural design, computational geometry, and GIS. Minimizing the area of their corresponding rectangular layouts is a key problem. We study the areaoptimization problem and show that it is NPhard t ..."
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Contact graphs of isothetic rectangles unify many concepts from applications including VLSI and architectural design, computational geometry, and GIS. Minimizing the area of their corresponding rectangular layouts is a key problem. We study the areaoptimization problem and show that it is NPhard to find a minimumarea rectangular layout of a given contact graph. We present O(n)time algorithms that construct O(n2)area rectangular layouts for general contact graphs and O(n log n)area rectangular layouts for trees. (For trees, this is an O(log n)approximation algorithm.) We also present an infinite family of graphs (rsp., trees) that require Ω(n2) (rsp., Ω(n log n)) area. We derive these results by presenting a new characterization of graphs that admit rectangular layouts using the related concept of rectangular duals. A corollary to our results relates the class of graphs that admit rectangular layouts to rectangle of influence drawings.