VLSI cell placement problem is known to be NP complete. A wide repertoire of heuristic algorithms exists in the literature for efficiently arranging the logic cells on a VLSI chip. The objective of this paper is to present a comprehensive survey of the various cell placement techniques, with emphasis on standard ce11and macro

Abstract — This paper presents a robust quadratic placement approach, which offers both high-quality placements and excellent computational efficiency. The additional force which distributes the modules on the chip in force-directed quadratic placement is separated into two forces: hold force and move force. Both of these forces are determined without any heuristics. Based on this novel systematic force implementation, we show that our iterative placement algorithm converges to an overlapfree placement. In addition, engineering change order (ECO) is efficiently supported by our placer. To handle the important trade-off between CPU time and placement quality, a deterministic quality control is presented. In addition, a new linear net model is proposed, which accurately models the half-perimeter wirelength (HPWL) in the quadratic cost function of quadratic placement. HPWL in general is a linear metric for netlength and represents an efficient and common estimation for routed wirelength. Compared with the classical clique net model, our linear net model reduces memory usage by 75%, CPUtimeby23 % and netlength by 8%, whichis measured by the HPWL of all nets. Using the ISPD-2005 benchmark suite for comparison, our placer combined with the new linear net model has just 5.9% higher netlength but is 16 × faster than APlace, which offers the best netlength in this benchmark. Compared to Capo, our placer has 9.2 % lower netlength and is 5.4 × faster. In the recent ISPD-2006 placement contest, in which quality is mainly determined by netlength and CPU time, our placer together with the new net model produced excellent results. 1.

A circuit layout problem requires determining the component pin placement and routing of interconnections for a given circuit schematic on a single or multilayer printed circuit board. In this paper, an integer programming based approach is introduced to solve the layout problem which performs placement and routing simultaneously. Since an integer programming problem is computationally intractable, a heuristic method to solve the placement and routing separately has been developed by utilizing the integer programming formulation. By applying a fixed routing scheme that connects components by direct line segments, the layout problem is transformed into a quadratic cost optimization problem in which the only decision variable is the pin placement, and which is solved by drawing an analogy between the quadratic cost term and the power dissipation term in a purely resistive network. Partitioning is then used to assign components to locations on a grid. Once the placement is determined, rou...

The growing complexity in the electronic hardware now necessitates in improving the performance of searching algorithms. Genetic algorithms do not guarantee global optimum solution to NP-Hard problems but are generally good at finding acceptable solution to problems. In complex combinatorial spaces, hybridization with other optimization techniques can greatly improve the efficiency of search. Memetic algorithm (MA) is an improvisation over genetic algorithms (GA) that combines global and local search by using evolutionary algorithms to perform exploration while the local search methods are used for exploitation. Here, exploitation is the process of visiting entirely new regions of a search space where the gain can also be high. This paper discusses the (MAs) as a solution to Standard Cell Placement (SCP) problem and procedures are laid down to strike a balance between genetic search and local search in MAs. A comparison of MA with the already established results for SCP using conventional and Hybrid techniques by the author depicts improvement in the performance of SCP algorithm in terms of solution quality and computing speed. About 15 % improvement in overall wire-length was observed along side it being 25% faster over the Tabu Search (TS) algorithm discussed in previous works of the author.