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472
Spectral Partitioning: The More Eigenvectors, the Better
 PROC. ACM/IEEE DESIGN AUTOMATION CONF
, 1995
"... The graph partitioning problem is to divide the vertices of a graph into disjoint clusters to minimize the total cost of the edges cut by the clusters. A spectral partitioning heuristic uses the graph's eigenvectors to construct a geometric representation of the graph (e.g., linear orderings) w ..."
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Cited by 77 (3 self)
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The graph partitioning problem is to divide the vertices of a graph into disjoint clusters to minimize the total cost of the edges cut by the clusters. A spectral partitioning heuristic uses the graph's eigenvectors to construct a geometric representation of the graph (e.g., linear orderings) which are subsequently partitioned. Our main result shows that when all the eigenvectors are used, graph partitioning reduces to a new vector partitioning problem. This result implies that as many eigenvectors as are practically possible should be used to construct a solution. This philosophy isincontrast to that of the widelyused spectral bipartitioning (SB) heuristic (which uses a single eigenvector to construct a 2way partitioning) and several previous multiway partitioning heuristics [7][10][16][26][37] (which usek eigenvectors to construct a kway partitioning). Our result motivates a simple ordering heuristic that is a multipleeigenvector extension of SB. This heuristic not only signi cantly outperforms SB, but can also yield excellent multiway VLSI circuit partitionings as compared to [1] [10]. Our experiments suggest that the vector partitioning perspective opens the door to new and effective heuristics.
Solving Steiner tree problems in graphs to optimality
 Networks
, 1998
"... Abstract: In this paper, we present the implementation of a branchandcut algorithm for solving Steiner tree problems in graphs. Our algorithm is based on an integer programming formulation for directed graphs and comprises preprocessing, separation algorithms, and primal heuristics. We are able to ..."
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Cited by 77 (3 self)
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Abstract: In this paper, we present the implementation of a branchandcut algorithm for solving Steiner tree problems in graphs. Our algorithm is based on an integer programming formulation for directed graphs and comprises preprocessing, separation algorithms, and primal heuristics. We are able to solve nearly all problem instances discussed in the literature to optimality, including one problem that—to our knowledge—has not yet been solved. We also report on our computational experiences with some very large Steiner tree problems arising from the design of electronic circuits. All test problems are gathered in a newly introduced library called SteinLib that is accessible via the World Wide Web. � 1998 John
HypergraphPartitioning Based Decomposition for Parallel SparseMatrix Vector Multiplication
 IEEE Trans. on Parallel and Distributed Computing
"... In this work, we show that the standard graphpartitioning based decomposition of sparse matrices does not reflect the actual communication volume requirement for parallel matrixvector multiplication. We propose two computational hypergraph models which avoid this crucial deficiency of the graph mo ..."
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Cited by 75 (35 self)
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In this work, we show that the standard graphpartitioning based decomposition of sparse matrices does not reflect the actual communication volume requirement for parallel matrixvector multiplication. We propose two computational hypergraph models which avoid this crucial deficiency of the graph model. The proposed models reduce the decomposition problem to the wellknown hypergraph partitioning problem. The recently proposed successful multilevel framework is exploited to develop a multilevel hypergraph partitioning tool PaToH for the experimental verification of our proposed hypergraph models. Experimental results on a wide range of realistic sparse test matrices confirm the validity of the proposed hypergraph models. In the decomposition of the test matrices, the hypergraph models using PaToH and hMeTiS result in up to 63% less communication volume (30%38% less on the average) than the graph model using MeTiS, while PaToH is only 1.32.3 times slower than MeTiS on the average. ...
Multilevel hypergraph partitioning
 Applications in VLSI design, ACM/IEEE Design Automation Conference
, 1997
"... Traditional hypergraph partitioning algorithms compute a bisection a graph such that the number of hyperedges that are cut by the partitioning is minimized and each partition has an equal number of vertices. The task of minimizing the cut can be considered as the objective and the requirement that t ..."
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Cited by 74 (4 self)
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Traditional hypergraph partitioning algorithms compute a bisection a graph such that the number of hyperedges that are cut by the partitioning is minimized and each partition has an equal number of vertices. The task of minimizing the cut can be considered as the objective and the requirement that the partitions will be of the same size can be considered as the constraint. In this paper we extend the partitioning problem by incorporating an arbitrary number of balancing constraints. In our formulation, a vector of weights is assigned to each vertex, and the goal is to produce a bisection such that the partitioning satisfies a balancing constraint associated with each weight, while attempting to minimize the cut. We present new multiconstraint hypergraph partitioning algorithms that are based on the multilevel partitioning paradigm. We experimentally evaluate the effectiveness of our multiconstraint partitioners on a variety of synthetically generated problems.
Dijkstra's Algorithm OnLine: An Empirical Case Study from Public Railroad Transport
 JOURNAL OF EXPERIMENTAL ALGORITHMICS
, 2000
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A Parallel Bottomup Clustering Algorithm with Applications to Circuit Partitioning in VLSI Design
 In Proc. ACM/IEEE Design Automation Conference
, 1993
"... In this paper, we present a bottomup clustering algorithm based on recursive collapsing of small cliques in a graph. The sizes of the small cliques are derived using random graph theory. This clustering algorithm leads to a natural parallel implementation in which multiple processors are used to id ..."
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Cited by 67 (9 self)
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In this paper, we present a bottomup clustering algorithm based on recursive collapsing of small cliques in a graph. The sizes of the small cliques are derived using random graph theory. This clustering algorithm leads to a natural parallel implementation in which multiple processors are used to identify clusters simultaneously. We also present a clusterbased partitioning method in which our clustering algorithm is used as a preprocessing step to both the bisection algorithm by Fiduccia and Mattheyses and a ratiocut algorithm by Wei and Cheng. Our results show that clusterbased partitioning obtains cut sizes up to 49.6% smaller than the bisection algorithm, and obtains ratio cut sizes up to 66.8% smaller than the ratiocut algorithm. Moreover, we show that clusterbased partitioning produces much stabler results than direct partitioning.
Defect tolerance in VLSI circuits: Techniques and yield analysis
 Proc. IEEE
, 1998
"... allows the manufacture of largearea integrated circuits with submicrometer feature sizes, enabling designs with several millions of devices. However, imperfections in the fabrication process result in yieldreducing manufacturing defects, whose severity grows proportionally with the size and densit ..."
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Cited by 67 (5 self)
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allows the manufacture of largearea integrated circuits with submicrometer feature sizes, enabling designs with several millions of devices. However, imperfections in the fabrication process result in yieldreducing manufacturing defects, whose severity grows proportionally with the size and density of the chip. Consequently, the development and use of yieldenhancement techniques at the design stage, to complement existing efforts at the manufacturing stage, is economically justifiable. Designstage yieldenhancement techniques are aimed at making the integrated circuit “defect tolerant, ” i.e., less sensitive to manufacturing defects. They include incorporating redundancy into the design, modifying the circuit floorplan, and modifying its layout. Successful designs of defecttolerant chips must rely on accurate yield projections. This paper reviews the currently used statistical yieldprediction models and their application to defecttolerant
Optimal Partitioners and Endcase Placers for Standardcell Layout
 IEEE TRANS. ON CAD
, 2000
"... We study alternatives to classic FMbased partitioning algorithms in the context of endcase processing for topdown standardcell placement. While the divide step in the topdown divide and conquer is usually performed heuristically, we observe that optimal solutions can be found for many su cientl ..."
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Cited by 63 (22 self)
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We study alternatives to classic FMbased partitioning algorithms in the context of endcase processing for topdown standardcell placement. While the divide step in the topdown divide and conquer is usually performed heuristically, we observe that optimal solutions can be found for many su ciently small partitioning instances. Our main motivation is that small partitioning instances frequently contain multiple cells that are larger than the prescribed partitioning tolerance, and that cannot be moved iteratively while preserving the legality ofa solution. To sample the suboptimality of FMbased partitioning algorithms, we focus on optimal partitioning and placement algorithms based on either enumeration or branchandbound that are invoked for instances below prescribed size thresholds,
Architectures and Algorithms for FieldProgrammable Gate Arrays with Embedded Memory
, 1997
"... Recent dramatic improvements in integrated circuit fabrication technology have led to FieldProgrammable Gate Arrays (FPGAs) capable of implementing entire digital systems, as opposed to the smaller logic circuits that have traditionally been targeted to FPGAs. Unlike the smaller circuits, these la ..."
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Cited by 60 (5 self)
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Recent dramatic improvements in integrated circuit fabrication technology have led to FieldProgrammable Gate Arrays (FPGAs) capable of implementing entire digital systems, as opposed to the smaller logic circuits that have traditionally been targeted to FPGAs. Unlike the smaller circuits, these large systems often contain memory. Architectural support for the efficient implementation of memory in nextgeneration FPGAs is therefore crucial. This dissertation examines the architecture of FPGAs with memory,aswell as algorithms that map circuits into these devices. Three aspects are considered: the analysis of circuits that contain memory as well as the automated random generation of such circuits, the architecture and algorithms for standalone con#gurable memory devices, and architect...
Solving Quadratic (0,1)Problems by Semidefinite Programs and Cutting Planes
, 1996
"... We present computational experiments for solving quadratic (0, 1) problems. Our approach combines a semidefinite relaxation with a cutting plane technique, and is applied in a Branch and Bound setting. Our experiments indicate that this type of approach is very robust, and allows to solve many moder ..."
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Cited by 60 (7 self)
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We present computational experiments for solving quadratic (0, 1) problems. Our approach combines a semidefinite relaxation with a cutting plane technique, and is applied in a Branch and Bound setting. Our experiments indicate that this type of approach is very robust, and allows to solve many moderately sized problems, having say, less than 100 binary variables, in a routine manner.