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The instructionset extension problem: A survey
 Reconfigurable Computing: Architectures, Tools and Applications, volume 4943 of Lecture Notes in Computer Science
, 2008
"... All intext references underlined in blue are linked to publications on ResearchGate, letting you access and read them immediately. ..."
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Cited by 12 (1 self)
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All intext references underlined in blue are linked to publications on ResearchGate, letting you access and read them immediately.
NearOptimal Instruction Selection on DAGs
, 2008
"... Instruction selection is a key component of code generation. High quality instruction selection is of particular importance in the embedded space where complex instruction sets are common and code size is a prime concern. Although instruction selection on tree expressions is a well understood and ea ..."
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Cited by 6 (2 self)
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Instruction selection is a key component of code generation. High quality instruction selection is of particular importance in the embedded space where complex instruction sets are common and code size is a prime concern. Although instruction selection on tree expressions is a well understood and easily solved problem, instruction selection on directed acyclic graphs is NPcomplete. In this paper we present NOLTIS, a nearoptimal, linear time instruction selection algorithm for DAG expressions. NOLTIS is easy to implement, fast, and effective with a demonstrated average code size improvement of 5.1 % compared to the traditional tree decomposition and tiling approach.
Minimizing VariableWeighted X3SAT
"... Abstract—In this paper, we present an upper bound of O(2 0.1625n) for the minimumweight exact 3satisfiability problem (MINWX3SAT) getting as input 3CNF formulas over n realvalued weighted propositional variables. This problem is NPhard and the best previous result is an exact algorithm solving ..."
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Abstract—In this paper, we present an upper bound of O(2 0.1625n) for the minimumweight exact 3satisfiability problem (MINWX3SAT) getting as input 3CNF formulas over n realvalued weighted propositional variables. This problem is NPhard and the best previous result is an exact algorithm solving MINWXSAT with no restrictions on clause length in
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"... Graph Covering for generating instruction specific application instructions: an overview of some existing methods ..."
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Graph Covering for generating instruction specific application instructions: an overview of some existing methods
Code Generation: On the Scheduling of DAGs Using WormPartition
"... Code generation consists of three main stages, instruction selection, scheduling and register allocation. The scheduling stage is very important because it affects the execution time of resulting code as well as the associated memory space needed to store the program. This paper deals with schedulin ..."
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Code generation consists of three main stages, instruction selection, scheduling and register allocation. The scheduling stage is very important because it affects the execution time of resulting code as well as the associated memory space needed to store the program. This paper deals with scheduling directed acyclic graphs (DAGs) using wormpartition. First, we develop a new algorithm to partition DAGs into a collection of worms while ensuring that the wormpartition is legal. Although the algorithm does not guarantee the minimum number of worms, it runs in optimal O(V  + E) time. This is in contrast to the known method [4] for producing the minimum number of worms that runs in O(V  2 + V E). We apply the algorithm to benchmark real problems and show its comparable results to the previous method. Then we study some DAG properties that are related to worm partitioning. We derive a necessary condition for the minimum number of worms in a given DAG. In other words, a lower bound for the number of worms. Then we identify two important classes of DAGs, for which this necessary condition is sufficient as well; i.e. we show that the lower bound is a tight one. Finally, we show that our algorithm generates the minimum number of worms for theses classes of DAGs. 1
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"... Graph Covering for generating instruction specific application instructions: an overview of some existing methods ..."
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Graph Covering for generating instruction specific application instructions: an overview of some existing methods
Acknowledgments
, 2004
"... This dissertation could not have been completed without significant help and input from two people. First, I would like to thank Dr. Ram (J. Ramanujam), who guided me with patience and accommodated my schedule to help me with this work. Second, I would like to thank Dr. Doris Carver, who steadfastly ..."
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This dissertation could not have been completed without significant help and input from two people. First, I would like to thank Dr. Ram (J. Ramanujam), who guided me with patience and accommodated my schedule to help me with this work. Second, I would like to thank Dr. Doris Carver, who steadfastly directed me towards this goal. I would also like to thank Dr. S. S. Iyengar, Dr. Donald E. Kraft, Dr. Jinpyo Hong, and Dr. Thomas Shaw for serving on my committee. I would be remiss if I did not mention the amount of time Dr. Ram and Dr. Hong spent on weekends discussing my work. Dr. Ram has the ability to discuss your ideas as if every one of them merits discussion. I am grateful for these discussions, some of which are chapters in this dissertation. Some of the work was expedited due to the use of “neato ” from ATT Research Labs and sample code for heuristics provided by Dr. Hong. Working full time while trying to pursue this degree required cooperation from my employers. Dr. Charles E. Graham and Mrs. Carol Wesson actively supported my pursuit. My appreciation for their support is heartfelt.
Instruction Reselection for Iterative Modulo Scheduling on High Performance Mutiissue DSPs
"... Abstract. An iterative modulo scheduling is more important for compilers targeting high performance multiissue digital signal processors than ever before because these processors are often severely limited by idle state functional units due to dependence constraint and thus the reduced the idle uni ..."
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Abstract. An iterative modulo scheduling is more important for compilers targeting high performance multiissue digital signal processors than ever before because these processors are often severely limited by idle state functional units due to dependence constraint and thus the reduced the idle units can have a positively significant impact on their performance. However, complex instructions, which are used in most recent DSPs such as mac, usually increase a data dependence complexity, and such complex dependencies that exist in signal processing applications often restrict modulo scheduling freedom and therefore, become a limiting factor of the iterative modulo scheduler. In this work, we propose a novel technique that efficiently reselect instructions of an application loop code considering with dependence complexity, which directly resolve the dependence constraint on a loop body, that are specifically featured for accelerating software pipelining performance by minimizing length of intrinsic cyclic dependencies in a loop code. To take advantage of this feature, few existing compilers support a loop unrolling based dependence relaxing technique, but only use them for some limited cases. This is mainly because the loop unrolling typically occurs an overhead of huge code size increment, and the iterative modulo scheduling with relaxed dependence techniques for general cases is an NPhard problem that necessitates complex assignments of registers and functional units in resource reservation table [8]. Our technique uses a heuristic to efficiently handle this problem in prestage of iterative modulo scheduling without loop unrolling. key words: code generation and optimization, application specific embedded software design, software pipelining, dependence analysis, high performance DSPs 1
NearOptimal Instruction Selection on DAGs
"... Instruction selection is a key component of code generation. High quality instruction selection is of particular importance in the embedded space where complex instruction sets are common and code size is a prime concern. Although instruction selection on tree expressions is a well understood and ea ..."
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Instruction selection is a key component of code generation. High quality instruction selection is of particular importance in the embedded space where complex instruction sets are common and code size is a prime concern. Although instruction selection on tree expressions is a well understood and easily solved problem, instruction selection on directed acyclic graphs is NPcomplete. In this paper we present NOLTIS, a nearoptimal, linear time instruction selection algorithm for DAG expressions. NOLTIS is easy to implement, fast, and effective with demonstrated average code size improvements of 1.48%. 1.
Tutor dr. ir. A. Augusteijn, Silicon Hive Supervisor dr. ir. C. Hemerik, TU/e Instruction Selection on Directed Acyclic Graphs
, 2007
"... Abstract i Wellknown techniques exist for optimal instruction selection based on treematching and dynamic programming. Such algorithms can optimally cover a tree of operations, representing a program under compilation, with treepatterns describing the semantics of target operations. These techniq ..."
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Abstract i Wellknown techniques exist for optimal instruction selection based on treematching and dynamic programming. Such algorithms can optimally cover a tree of operations, representing a program under compilation, with treepatterns describing the semantics of target operations. These techniques work well for intermediate representations based on trees where linear time solutions exist. However, more modern internal representations in compilers are based on data flow graphs, which describe a DAG (directed acyclic graph) of operations. Also, more complex target operations can have semantics that need to be described using DAGs instead of trees. Certain basic assumptions in optimal tree pattern matching (which enable dynamic programming and hence efficient implementations) break down when being generalized to DAGs. The Silicon Hive compiler uses a dataflow graph as its intermediate representation. The semantics of target operations are described in a machine description which is interpreted by the instruction selection. Such semantics can be arbitrary DAGs. This report will focus on DAGbased pattern matching, especially in making a survey of existing