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An Industrially Effective Environment for Formal Hardware Verification
 IEEE TCAD
, 2005
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Putting it all together — Formal Verification of the VAMP
 International Journal on Software Tools for Technology Transfer (STTT
"... Abstract. In the VAMP (verified architecture microprocessor) project we have designed, functionally verified, and synthesized a processor with full DLX instruction set, delayed branch, Tomasulo scheduler, maskable nested precise interrupts, pipelined fully IEEE compatible dual precision floating poi ..."
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Cited by 29 (3 self)
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Abstract. In the VAMP (verified architecture microprocessor) project we have designed, functionally verified, and synthesized a processor with full DLX instruction set, delayed branch, Tomasulo scheduler, maskable nested precise interrupts, pipelined fully IEEE compatible dual precision floating point unit with variable latency, and separate instruction and data caches. The verification has been carried out in the theorem proving system PVS. The processor has been implemented on a Xilinx FPGA. 1
A summary of intrinsic partitioning verification
 In In Proceedings of the Fifth International Workshop on the ACL2 Theorem Prover and Its Applications (ACL2
, 2004
"... Successful formal methods applications have four characteristics: intrinsically important applications, concise correctness theorems, validated models, and proof automation. We describe a recentlycompleted verification of a microprocessor's intrinsic partitioning mechanism in those terms. What ..."
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Cited by 20 (4 self)
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Successful formal methods applications have four characteristics: intrinsically important applications, concise correctness theorems, validated models, and proof automation. We describe a recentlycompleted verification of a microprocessor's intrinsic partitioning mechanism in those terms. What Makes for a Good Application of Formal Methods? Formal methods is the application of mathematical reasoning to establish properties about digital systems. Formal methods can be applied in many different ways with many different notations and tools. They can deal with system models that describe the lowest level of implementation or the most abstract requirements, with properties to be proved that may be comprehensive descriptions of “correctness ” or minor aspects that indicate good system development. Despite the wide range of formal methods applications, we observe that successful formal methods projects share four characteristics. 1. The target being analyzed is intrinsically important. Formal methods can provide a high level of certainty about a target, but the extra assurance must be worth the effort that formal verification usually entails. Three applications of formal methods that we consider successful are Microsoft’s SLAM project [Ball2004], AMD’s floatingpoint verification [Russinoff2000], and Rockwell Collins ’ requirements validation [Miller2004]. The SLAM project aims to reduce crashes of Microsoft’s Windows OS by proving important device driver behaviors. AMD’s floatingpoint work seeks to eliminate errors in the floatingpoint units on AMD's x86 microprocessors. Rockwell Collins is applying modelchecking to help validate requirements for safetycritical systems. Each of these applications of formal methods is solving a problem that is important enough to justify an extra effort. 2. The target’s desired behavior has a concise and understandable formalization. An important indicator of successful formal methods application is the degree to which the description of the needed property is compelling. A proved theorem only increases assurance about a target of evaluation if we trust in the formalization of the desired
Formal Verification of the VAMP Floating Point Unit
 In CHARME 2001, volume 2144 of LNCS
, 2001
"... We report on the formal verification of the floating point unit used in the VAMP processor. The FPU is fully IEEE compliant, and supports denormals and exceptions in hardware. The supported operations are addition, subtraction, multiplication, division, comparison, and conversions. The hardware is v ..."
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Cited by 17 (6 self)
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We report on the formal verification of the floating point unit used in the VAMP processor. The FPU is fully IEEE compliant, and supports denormals and exceptions in hardware. The supported operations are addition, subtraction, multiplication, division, comparison, and conversions. The hardware is verified on the gate level against a formal description of the IEEE standard by means of the theorem prover PVS.
Instantiating uninterpreted functional units and memory system: Functional verification of the VAMP
 Correct Hardware Design and Verification Methods, volume 2860 of Lecture Notes in Computer Science
, 2003
"... Abstract. In the VAMP (verified architecture microprocessor) project we have designed, functionally verified, and synthesized a processor with full DLX instruction set, delayed branch, Tomasulo scheduler, maskable nested precise interrupts, pipelined fully IEEE compatible dual precision floating poi ..."
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Cited by 14 (8 self)
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Abstract. In the VAMP (verified architecture microprocessor) project we have designed, functionally verified, and synthesized a processor with full DLX instruction set, delayed branch, Tomasulo scheduler, maskable nested precise interrupts, pipelined fully IEEE compatible dual precision floating point unit with variable latency, and separate instruction and data caches. The verification has been carried out in the theorem proving system PVS. The processor has been implemented on a Xilinx FPGA. 1
Automatic formal verification of fusedmultiplyadd FPUs
 in DATE
, 2005
"... In this paper we describe a fullyautomated methodology for formal verification of fusedmultiplyadd floating point units (FPUs). Our methodology verifies an implementation FPU against a simple reference model derived from the processor’s architectural specification, which may include all aspects o ..."
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Cited by 13 (5 self)
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In this paper we describe a fullyautomated methodology for formal verification of fusedmultiplyadd floating point units (FPUs). Our methodology verifies an implementation FPU against a simple reference model derived from the processor’s architectural specification, which may include all aspects of the IEEE specification including denormal operands and exceptions. Our strategy uses a combination of BDD and SATbased symbolic simulation. To make this verification task tractable, we use a combination of casesplitting, multiplier isolation, and automatic model reduction techniques. The casesplitting is defined only in terms of the reference model, which makes this approach easily portable to new designs. The methodology is directly applicable to multiGHz industrial implementation models (e.g., HDL or gatelevel circuit representations) that contain all details of the highperformance transistorlevel model, such as aggressive pipelining, clocking, etc. Experimental results are provided to demonstrate the computational efficiency of this approach. 1
Formal Verification of a Theory of IEEE Rounding
 TPHOLs 2001: Supplemental Proceedings, Informatics Research Report EDIINFRR0046
, 2001
"... We report on the formal verification of a theory of IEEE rounding in the theorem prover PVS. The theory consists of a formalization of the IEEE standard, and notations and theorems facilitating the verification of floating point hardware. In particular, the concepts of #equivalence and round dec ..."
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Cited by 6 (1 self)
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We report on the formal verification of a theory of IEEE rounding in the theorem prover PVS. The theory consists of a formalization of the IEEE standard, and notations and theorems facilitating the verification of floating point hardware. In particular, the concepts of #equivalence and round decomposition are formalized, allowing for a subdivision of floating point units into smaller building blocks, which then can be verified separately. The theory has been successfully applied to the verification of a fully IEEE compliant floating point unit.
A Flexible Formal Verification Framework for Industrial Scale Validation
 In: Memocode ’11, IEEE
, 2011
"... Abstract—In recent years, leading microprocessor companies have made huge investments to improve the reliability of their products. Besides expanding their validation and CAD tools teams, they have incorporated formal verification methods into their design flows. Formal verification (FV) engineers r ..."
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Cited by 5 (1 self)
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Abstract—In recent years, leading microprocessor companies have made huge investments to improve the reliability of their products. Besides expanding their validation and CAD tools teams, they have incorporated formal verification methods into their design flows. Formal verification (FV) engineers require extensive training, and FV tools from CAD vendors are expensive. At first glance, it may seem that FV teams are not affordable by smaller companies. We have not found this to be true. This paper describes the formal verification framework we have built on top of publiclyavailable tools. This framework gives us the flexibility to work on myriad different problems that occur in microprocessor design. I.
Formal Verification of Microprocessors at AMD
 Proceedings of the 4 th International Workshop on Designing Correct Circuits (DCC 2002
, 2002
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Formal Verification of FloatingPoint RTL at AMD Using the ACL2 Theorem Prover
"... Abstract We describe a methodology for the formal verification of the correctness, including IEEEcompliance, of registertransfer level models of floatingpoint hardware designs, and its application to the floatingpoint units of a series of commercial microprocessors produced by Advanced Micro De ..."
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Cited by 3 (0 self)
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Abstract We describe a methodology for the formal verification of the correctness, including IEEEcompliance, of registertransfer level models of floatingpoint hardware designs, and its application to the floatingpoint units of a series of commercial microprocessors produced by Advanced Micro Devices, Inc. The methodology is based on a mechanical translator from a synthesizable subset of the Verilog hardware description language, in which the models are coded, to the formal logic of the ACL2 theorem prover. Behavioral specifications of correctness, coded in essentially the same language as the designs, are translated as well, and ultimately checked with the ACL2 prover. Keywords — Formal verification, Floatingpoint arithmetic, IEEEcompliance, Theorem proving, ACL2