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23
An Exact Solution to the Transistor Sizing Problem for CMOS Circuits Using Convex Optimization
 IEEE Transactions on ComputerAided Design
, 1993
"... this paper. Given the MOS circuit topology, the delay can be controlled byvarying the sizes of transistors in the circuit. Here, the size of a transistor is measured in terms of its channel width, since the channel lengths in a digital circuit are generally uniform. Roughly speaking, the sizes of ..."
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Cited by 91 (19 self)
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this paper. Given the MOS circuit topology, the delay can be controlled byvarying the sizes of transistors in the circuit. Here, the size of a transistor is measured in terms of its channel width, since the channel lengths in a digital circuit are generally uniform. Roughly speaking, the sizes of certain transistors can be increased to reduce the circuit delay at the expense of additional chip area
Timing verification and the Timing Analysis program
 Proc., IEEE/ACM DAC
, 1982
"... Timing Verification consists of validating the path delays (primary input or storage element to primary output or storage element) to be sure they are not too long or too short and checking the clock pulses to be sure they are not too wide or too narrow. The programs addressing these problems neithe ..."
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Cited by 55 (0 self)
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Timing Verification consists of validating the path delays (primary input or storage element to primary output or storage element) to be sure they are not too long or too short and checking the clock pulses to be sure they are not too wide or too narrow. The programs addressing these problems neither produce input patterns like test pattern generators nor require input patterns like traditional simulators. Several programs (described here) operate by tracing paths [Pl73, WO78, SA81, KA81]. One program [MC80] extends simulation into a pessimistic analyzer not dependent on test patterns. Timing Analysis, a program described recently in [HI82a], is designed to analyze the timing of large digital computers and is based, in part, on the concepts disclosed in a patented method [DO81] for determining the extreme characteristics of logic block diagrams. The output of Timing Analysis includes "slack " at each block to provide a measure of the severity of the timing problem. The program also generates standard deviations for the times so that a statistical timing design can be produced rather than a worst case approach. 1. All internal paths, which can be activated from storage element or PI to storage element or PO, w i l l have delays neither too long nor too short (Figure I). 2. All clock signals propagating though the repowering c i rcu i t ry w i l l retain the required minimum pulse width despite the shrinking effect of nonsymmetric delays (Figure 2). CLOCK i
Statistical Timing Analysis Under Spatial Correlations
 IEEE Transactions on ComputerAided Design of Integrated Circuits and Systems
, 2005
"... Abstract — Process variations are of increasing concern in today’s technologies, and can significantly affect circuit performance. We present an efficient statistical timing analysis algorithm that predicts the probability distribution of the circuit delay considering both interdie and intradie va ..."
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Cited by 46 (5 self)
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Abstract — Process variations are of increasing concern in today’s technologies, and can significantly affect circuit performance. We present an efficient statistical timing analysis algorithm that predicts the probability distribution of the circuit delay considering both interdie and intradie variations, while accounting for the effects of spatial correlations of intradie parameter variations. The procedure uses a firstorder Taylor series expansion to approximate the gate and interconnect delays. Next, principal component analysis techniques are��and ��� are employed to transform the set of correlated parameters into an uncorrelated set. The statistical timing computation is then easily performed with a PERTlike circuit graph traversal. The runtime of our algorithm is linear in the number of gates and interconnects, as well as the number of varying parameters and grid partitions that are used to model spatial correlations. The accuracy of the method is verified with Monte Carlo simulation. On average, for 100nm technology, the errors of mean and standard deviation values computed by the proposed method respectively, and the errors of predicting the��and confidence point are ���and ���respectively. A testcase with about 17,800 gates was solved in about�seconds, with high accuracy as compared to a Monte Carlo simulation that required more than�hours.
Timing and Area Optimization for StandardCell VLSI Circuit Design
, 1995
"... A standard cell library typically contains several versions of any given gate type, each of which has a different gate size. We consider the problem of choosing optimal gate sizes from the library to minimize a cost function (such as total circuit area) while meeting the timing constraints imposed o ..."
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Cited by 16 (1 self)
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A standard cell library typically contains several versions of any given gate type, each of which has a different gate size. We consider the problem of choosing optimal gate sizes from the library to minimize a cost function (such as total circuit area) while meeting the timing constraints imposed on the circuit. After
Timing Analysis in Presence of Power Supply and Ground Voltage Variation
 IN IEEE/ACM INTERNATIONAL CONFERENCE ON COMPUTERAIDED DESIGN
, 2003
"... Given the sensitivity of circuit delay to supply and ground voltage values, static timing analysis (STA) must take into account supply voltage variations. Existing STA techniques allow one to verify the timing at different process corners which effectively only considers cases where all the supplies ..."
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Cited by 9 (5 self)
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Given the sensitivity of circuit delay to supply and ground voltage values, static timing analysis (STA) must take into account supply voltage variations. Existing STA techniques allow one to verify the timing at different process corners which effectively only considers cases where all the supplies are low or all are high. Cases of mismatch between the supplies of driver and load are not considered. In practice, supply voltages are neither totally independent nor totally dependent. In this work, we consider the supply and ground nodes of a logic gate to be either totally independent variables, or to be directly tied or connected to those of some other gate(s) in the circuit. We also assume that the exact supply voltage values are not known exactly, but that only upper/lower bounds on them are known. In this framework, we propose new timing models for logic gates and identify the worstcase voltage configurations for individual gates and for simple paths. We then give an STA technique that provides the worstcase circuit delay taking supply variations into account.
Cycletime Aware Architecture Synthesis of Custom Hardware Accelerators
 In: Proceedings of International Conference on Compilers, Architecture. and Synthesis for Embedded Systems (CASES
, 2002
"... We present the cycletime aware architecture synthesis methodology used in PICONPA that automatically synthesizes minimal cost RTlevel designs from highlevel specifications to meet a given cycletime. This allows subsequent physical synthesis to succeed on first pass with predictable performance. ..."
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Cited by 8 (0 self)
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We present the cycletime aware architecture synthesis methodology used in PICONPA that automatically synthesizes minimal cost RTlevel designs from highlevel specifications to meet a given cycletime. This allows subsequent physical synthesis to succeed on first pass with predictable performance. The core of the methodology is a static timing analysis engine that is used at multiple levels  programlevel, architecturelevel and RTlevel  in order to identify, schedule and validate useful operator chains that are incorporated into the design automatically. We present architecture synthesis results for several embedded applications and evaluate the benefits of this technique.
Timing Analysis in HighLevel Synthesis
, 1992
"... ... for behaviorallevel specifications and algorithms for timing analysis in highlevel synthesis. It is based on a timing network which models the data flow as well as the control flow in the behavioral input specification. The delay values for the network modules are created by invoking the same ..."
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Cited by 7 (0 self)
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... for behaviorallevel specifications and algorithms for timing analysis in highlevel synthesis. It is based on a timing network which models the data flow as well as the control flow in the behavioral input specification. The delay values for the network modules are created by invoking the same logic synthesis procedure applied after behavioral synthesis. The timing network is built only once for a given behavioral description. Several parameters are used to explore di#erent scheduling possibilities as well as di#erent optimization modes (area, delay), without changing the network. The use of the timing model in conjunction with a pathbased scheduling algorithm is presented. Results for several benchmarks attested the accuracy of this approach.
A Scalable Statistical Static Timing Analyzer Incorporating Correlated NonGaussian and Gaussian Parameter Variations
"... We propose a scalable and efficient parameterized blockbased statistical static timing analysis (SSTA) algorithm incorporating both Gaussian and nonGaussian parameter distributions, capturing spatial correlations using a gridbased model. As a preprocessing step, we employ independent component an ..."
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Cited by 2 (1 self)
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We propose a scalable and efficient parameterized blockbased statistical static timing analysis (SSTA) algorithm incorporating both Gaussian and nonGaussian parameter distributions, capturing spatial correlations using a gridbased model. As a preprocessing step, we employ independent component analysis to transform the set of correlated nonGaussian parameters to a basis set of parameters that are statistically independent, and principal components analysis to orthogonalize the Gaussian parameters. Given the moments of the variational parameters, we use a Padé approximationbased moment matching scheme to generate the distributions of the random variables representing the signal arrival times, and preserve correlation information by propagating arrival times in a canonical form. Our experiments reveal that for the cases, when the sensitivities of Gaussian parameters outweigh that of the nonGaussian parameters, a Gaussian SSTA proves to be reasonably accurate. However, for the cases when the nonGaussian parameter sensitivities dominate the Gaussians, modeling all parameters as normal leads to significant inaccuracies in the SSTA results. For both cases, our SSTA procedure is able to generate the circuit delay distributions with reasonably small prediction errors. For the ISCAS89 benchmark circuits, as compared to Monte Carlo simulations, we obtain average errors of 0.99%, 2.05%, 2.33 % and 2.36%, respectively, in the mean, standard deviation, 5 % and 95 % quantile points of the circuit delay. Experimental results show that our procedure can handle as many as 256 correlated nonGaussian variables in about 5 minutes of run time. For a circuit with G  gates and a layout with g spatial correlation grids, the complexity of our approach is O(gG). I.
Efficient Calculation of AllPairs InputtoOutput Delays in Synchronous Sequential Circuits
"... In this paper, we consider the problem of finding allpairs inputtooutput delays for combinational circuits. This method is of practical utility in several design situations and CAD algorithms, for example in [1, 2]. An algorithm for solving this problem was proposed in [1]; however, this can be c ..."
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Cited by 2 (1 self)
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In this paper, we consider the problem of finding allpairs inputtooutput delays for combinational circuits. This method is of practical utility in several design situations and CAD algorithms, for example in [1, 2]. An algorithm for solving this problem was proposed in [1]; however, this can be computationally expensive. We take advantage of some properties of large realistic circuits to present an algorithm that is two orders of magnitude faster than the method in [1] for large circuits. Experimental results on ISCAS benchmark circuits prove the efficacy of this approach.
Modular compilation of a synchronous language
 Research Report 6424, INRIA
"... Abstract Synchronous languages rely on formal methods to ease the development of applications in an efficient and reusable way. Formal methods have been advocated as a means of increasing the reliability of systems, especially those which are safety or business critical. It is still difficult to dev ..."
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Cited by 2 (0 self)
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Abstract Synchronous languages rely on formal methods to ease the development of applications in an efficient and reusable way. Formal methods have been advocated as a means of increasing the reliability of systems, especially those which are safety or business critical. It is still difficult to develop automatic specification and verification tools due to limitations like state explosion, undecidability, etc... In this work, we design a new specification model based on a reactive synchronous approach. Then, we benefit from a formal framework well suited to perform compilation and formal validation of systems. In practice, we design and implement a special purpose language (LE) and its two semantics: the behavioral semantics helps us to define a program by the set of its behaviors and avoid ambiguousness in programs ’ interpretation; the execution equational semantics allows the modular compilation of programs into software and hardware targets (C code, Vhdl code, Fpga synthesis, Verification tools). Our approach is pertinent considering the two main requirements of critical realistic applications: the modular compilation allows us to deal with large systems, the modeldriven approach provides us with formal validation. keywords: modeldriven language, synchronous models, compilation, modularity, verification