Results 1  10
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78
Timing Driven Placement for Large Standard Cell Circuits
 Proc. DAC
, 1995
"... We present an algorithm for accurately controlling delays during the placement of large standard cell integrated circuits. Previous approaches to timing driven placement could not handle circuits containing 20,000 or more cells and yielded placement qualities which were well short of the state of th ..."
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Cited by 81 (1 self)
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We present an algorithm for accurately controlling delays during the placement of large standard cell integrated circuits. Previous approaches to timing driven placement could not handle circuits containing 20,000 or more cells and yielded placement qualities which were well short of the state of the art. Our timing optimization algorithm has been added to the placement algorithm which has yielded the best results ever reported on the full set of MCNC benchmark circuits, including a circuit containing more than 100,000 cells. A novel pinpair algorithm controls the delay without the need for user path specification. The timing algorithm is generally applicable to hierarchical, iterative placement methods. Using this algorithm, we present results for the only MCNC standard cell benchmark circuits (fract, struct, and avq.small) for which timing information is available. We decreased the delay of the longest path of circuit fract by 36 % at an area cost of only 2.5%. For circuit struct, the delay of the longest path was decreased by 50 % at an area cost of 6%. Finally, for the large (22,000 cell) circuit avq.small, the longest path delay was decreased by 28 % at an area cost of 6 % yet only doubling the execution time. This is the first report of timing driven placement results for any MCNC benchmark circuit. 2.
Noise in deep submicron digital design
 in Proc. of the International Conference on ComputerAided Design (ICCAD
, 1996
"... As technology scales into the deep submicron regime, noise immunity is becoming a metric of comparable importance to area, timing, and power for the analysis and design of VLSI systems. This paper denes noise as it pertains to digital systems and addresses the technology trends which are bringing n ..."
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Cited by 78 (6 self)
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As technology scales into the deep submicron regime, noise immunity is becoming a metric of comparable importance to area, timing, and power for the analysis and design of VLSI systems. This paper denes noise as it pertains to digital systems and addresses the technology trends which are bringing noise issues to the forefront. The noise sources which are plaguing digital systems are explained. A metric referred to as noise stability is dened, and a static noise analysis methodology based on this metric is introduced to demonstrate how noise can be analyzed systematically. Analysis issues associated with onchip interconnect are also considered. This paper concludes with a discussion of the device, circuit, layout, and logic design issues associated with noise. 1
Death, Taxes and Failing Chips
, 2003
"... In the way they cope with variability, presentday methodologies are onerous, pessimistic and risky, all at the same time! Dealing with variability is an increasingly important aspect of highperformance digital integrated circuit design, and indispensable for firsttimeright hardware and cuttinged ..."
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Cited by 63 (3 self)
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In the way they cope with variability, presentday methodologies are onerous, pessimistic and risky, all at the same time! Dealing with variability is an increasingly important aspect of highperformance digital integrated circuit design, and indispensable for firsttimeright hardware and cuttingedge performance. This invited paper discusses the methodology, analysis, synthesis and modeling aspects of this problem. These aspects of the problem are compared and contrasted in the ASIC and custom (microprocessor) domains. This paper pays particular attention to statistical timing analysis and enumerates desirable attributes that would render such an analysis capability practical and accurate.
Statistical Delay Calculation, a Linear Time Method
, 1997
"... This paper discusses a statistical approach to static timing analysis. Delays of gates and wires are modeled by stochastic values instead of the triple best case, typical and worst case delay. This has the advantage of avoiding the overly pessimistic (optimistic) outcome of traditional worst (best) ..."
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Cited by 46 (1 self)
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This paper discusses a statistical approach to static timing analysis. Delays of gates and wires are modeled by stochastic values instead of the triple best case, typical and worst case delay. This has the advantage of avoiding the overly pessimistic (optimistic) outcome of traditional worst (best) case calculations. The paper proposes a new approximate scheme to perform the delay calculations with stochastic delay values in linear time. The results are validated with Monte Carlo simulations. From a mathematical analysis some counterintuitive properties of delays in the presence of uncertain delay values are shown. The results section shows that that traditional worstcase timing analysis is on average 21% too pessimistic for the set of IWLS '91 combinational benchmark circuits for a given delay model. Also, it is shown that the traditional typical delay calculation underestimates the most likely circuit delay by 0  14%. Furthermore, due to the mathematical properties of the delay...
Harmony: Static Noise Analysis of Deep Submicron Digital Integrated Circuits
 IEEE Trans. CAD
, 1999
"... As technology scales into the deep submicron regime, noise immunity is becoming a metric of comparable importance to area, timing, and power for the analysis and design of very large scale integrated (VLSI) systems. A metric for noise immunity is defined, and a static noise analysis methodology base ..."
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Cited by 31 (5 self)
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As technology scales into the deep submicron regime, noise immunity is becoming a metric of comparable importance to area, timing, and power for the analysis and design of very large scale integrated (VLSI) systems. A metric for noise immunity is defined, and a static noise analysis methodology based on this noisestability metric is introduced to demonstrate how noise can be analyzed systematically on a fullchip basis using simulationbased transistorlevel analysis. We then describe Harmony, a twolevel (macro and global) hierarchical implementation of static noise analysis. At the macro level, simplified interconnect models and timing assumptions guide efficient analysis. The global level involves a careful combination of static noise analysis, static timing analysis, and detailed interconnect macromodels based on reducedorder modeling techniques. We describe how the interconnect macromodels are practically employed to perform coupling analysis and how timing constraints can be use...
Timingdriven placement based on partitioning with dynamic cutnet control
 In ACM/IEEE Design Automation Conference (DAC
, 2000
"... This paper presents a partitioningbased, timingdriven placement algorithm. The partitioning step itself is timingdriven and based on solving a quadratic programming problem iteratively. The placement algorithm does not rely on interleaved timing calculations, which tend to be inaccurate. Instead, ..."
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Cited by 28 (1 self)
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This paper presents a partitioningbased, timingdriven placement algorithm. The partitioning step itself is timingdriven and based on solving a quadratic programming problem iteratively. The placement algorithm does not rely on interleaved timing calculations, which tend to be inaccurate. Instead, it achieves the desired result by controlling the number of times that a path in the circuit can be cut. In addition to the cutting constraint, a prelocking mechanism and timingaware terminal propagation are developed and integrated into the flow. The detailed placement step is formulated as a constrained quadratic program and solved efficiently. Results show improvements of 23.41 % on average compared to another timingdriven placement system TimingQUAD and significant improvements over Eisenmann’s placement algorithm. 1.
On Path Selection In Combinational Logic Circuits
, 1989
"... In order to ascertain correct operation of digital logic circuits it is necessary to verify correct functional operation as well as correct operation at desired clock rates. To ascertain correct operation at desired clock rates signal propagation delays along a set of selected paths are verified to ..."
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Cited by 27 (2 self)
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In order to ascertain correct operation of digital logic circuits it is necessary to verify correct functional operation as well as correct operation at desired clock rates. To ascertain correct operation at desired clock rates signal propagation delays along a set of selected paths are verified to fall within allowed limits by applying appropriate stimuli. Earlier it was suggested that an appropriate set of paths to test would be the one that includes at least one path, with maximum modeled delay, for each circuit lead or gate input. In this paper, algorithms to select such sets of paths with minimum cardinality are given.
MinMax Placement for LargeScale Timing Optimization
 In ACM International Symposium on Physical Design
, 2002
"... With featuresizes below 0�25µm, interconnect delays account for over 40 % of worst delays [12]. Transitions to 0�18µm and 0�13µm further increase this figure, and thus the relative importance of timingdriven placement for VLSI. Our work introduces a novel minimization of maximal path delay that im ..."
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Cited by 24 (8 self)
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With featuresizes below 0�25µm, interconnect delays account for over 40 % of worst delays [12]. Transitions to 0�18µm and 0�13µm further increase this figure, and thus the relative importance of timingdriven placement for VLSI. Our work introduces a novel minimization of maximal path delay that improves upon previously known algorithms for timingdriven placement. Our placement algorithms have provable properties and are fast in practice. Our empirical validation is based on extending a scalable mincut placer with proven empirical record in wirelength and congestiondriven placement [4]. The overhead of timingdriven placement was within 50 % CPU time. We placed industrial circuits and evaluated the layouts with a commercial static timing analyzer.
Conquering Noise in DeepSubmicron Digital ICs
, 1998
"... duction in the top and bottom areas of a minimumwidth wire means that total wire capacitance is decreasing. Resistance, however, is increasing faster, despite efforts not to scale metal thicknesses. Moreover, the fraction of selfcapacitance represented by lateral coupling is increasing. Die size ..."
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Cited by 18 (0 self)
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duction in the top and bottom areas of a minimumwidth wire means that total wire capacitance is decreasing. Resistance, however, is increasing faster, despite efforts not to scale metal thicknesses. Moreover, the fraction of selfcapacitance represented by lateral coupling is increasing. Die sizes remain relatively constant as more functionality is integrated on a single chip. Consequently, average wire lengths are also relatively constant, despite the decreasing pitch. These geometry factors have already made RC (resistancecapacitance) delays in the interconnect a significant performance component. These trends, combined with faster onchip slew times, also mean that capacitive coupling is becoming a significant source of noise. Furthermore, in many cases, because of this coupling capacitance,. one cannot accurately calculate delay without considering the effect of simultaneous switching on coupled nets. Practical efforts to control RC delays through the use of lowresistivity