this paper. Given the MOS circuit topology, the delay can be controlled byvarying the sizes of transistors in the circuit. Here, the size of a transistor is measured in terms of its channel width, since the channel lengths in a digital circuit are generally uniform. Roughly speaking, the sizes of certain transistors can be increased to reduce the circuit delay at the expense of additional chip area

The effect of interconnect coupling capacitance on the transient characteristics of a CMOS logic gate strongly depends upon the signal activity. A transient analysis of CMOS logic gates driving two and three coupled resistive-capacitive interconnect lines is presented in this paper for different signal combinations. Analytical expressions characterizing the output voltage and the propagation delay of a CMOS logic gate are presented for a variety of signal activity conditions. The uncertainty of the effective load capacitance on the propagation delay due to the signal activity is also addressed. It is demonstrated that the effective load capacitance of a CMOS logic gate depends upon the intrinsic load capacitance, the coupling capacitance, the signal activity, and the size of the CMOS logic gates within a capacitively coupled system. Some design strategies are also suggested to reduce the peak noise voltage and the propagation delay caused by the interconnect coupling capacitance.

Excessive voltage drops in power and ground (P&G) buses of CMOS VLSI circuits can severely degrade both design reliability and performance. Maximum current estimates are needed in the circuit to accurately determine the impact of these problems. In [1], a pattern-independent, linear time algorithm (iMax) is described that is very effective in estimating the maximum current waveforms at various contact points in the circuit. In [1], the algorithm was demonstrated for simple gate delay and current models. In this paper, we first derive expressions for modeling delays and current waveforms for a general gate and then describe how the algorithm can be extended under more general models. 1 Introduction In the design and analysis of high performance VLSI circuits, reliability considerations are extremely important and should be considered early in the design phase. Excessive currents in power and ground (P&G) buses of CMOS circuits affect both circuit reliability and performance by causing...

this paper. Key factors that determine the operation of a gate, such as the di!erent modes of operation of serially connected transistors, the starting point of conduction, the parasitic behaviour of the shortcircuiting block of a gate and the behaviour of parallel transistor structures are analysed and properly modelled. The analysis is performed taking into account second-order e!ects of short-channel devices and for non-zero transition time inputs. Analytical expressions for the output waveform, the propagation delay and the short-circuit power dissipation are obtained by solving the di!erential equations that govern the operation of the gate. The calculated results are in excellent agreement with SPICE simulations. Copyright # 1999 John Wiley & Sons, Ltd

An accurate and efficient method for modelling CMOS gates by a single equivalent transistor is...

Trends in CMOS Technology and VLSI architectures are causing interconnect to play an increasing role in overall performance and power consumption. Repeaters are a classical approach to managing interconnect delay and are now commonly used for interconnect planning and global routing (both manually and in CAD tools). By automating repeater placement in the inner loop of a CAD tool, much more aggressive timing goals can be targeted early in the design process. However the classical approaches to repeater insertion (number, spacing and sizing) are increasingly inadequate due to 1) short-channel devices, 2) resistance, coupling and inductance in interconnects and 3) constraints on the placement of the repeaters. In this paper, we use a new short-channel MOS delay model to develop closed-form expressions for repeater insertion parameters. In particular, we focus on the effects of repeater placement constraints on the overall delay of the repeated interconnect. We show how worst-case placement scenarios can actually arise in realistic VLSI floorplans resulting in significant variation in the delay. We then explore methods of mitigating these eddects by adjusting the number and sizing of the repeaters. Closed form expressions for all design parameters can be used to develop repeater insertion utilities as part of a larger interconnect planning or global routing tool. Our analytical delay models for a wide range of repeater chains have been veridied to be within 5% of SPICE simulations of a commercial 0.13µm CMOS technology.

A high drive CMOS buffer circuit characterized by a voltage transfer characteristic (VTC) with low threshold voltages and hysteresis is proposed. The proposed circuit is capable of restoring slow transition times and distorted input signals with a minimum delay penalty. Due to the hysteresis characteristic of this buffer, a comparison with a Schmitt-trigger is provided. An important application of this circuit is the restoration of slow transitioning signals propagated along an RC interconnect. The circuit can be used in conjunction with existing repeater insertion methodologies to decrease the delay of an RC line.

A novel approach for obtaining the output waveform, the propagation delay...

Given the sensitivity of circuit delay to supply and ground voltage values, static timing analysis (STA) must take into account supply voltage variations. Existing STA techniques allow one to verify the timing at di#erent process corners which e#ectively only considers cases where all the supplies are low or all are high. Cases of mismatch between the supplies of driver and load are not considered. In practice, supply voltages are neither totally independent nor totally dependent. In this work, we consider the supply and ground nodes of a logic gate to be either totally independent variables, or to be directly tied or connected to those of some other gate(s) in the circuit. We also assume that the exact supply voltage values are not known exactly, but that only upper/lower bounds on them are known. In this framework, we propose new timing models for logic gates and identify the worst-case voltage configurations for individual gates and for simple paths. We then give an STA technique that provides the worst-case circuit delay taking supply variations into account.