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PartialOrder Reduction in Symbolic State Space Exploration
, 1997
"... . State space explosion is a fundamental obstacle in formal verification of designs and protocols. Several techniques for combating this problem have emerged in the past few years, among which two are significant: partialorder reductions and symbolic state space search. In asynchronous systems, ..."
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Cited by 59 (0 self)
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. State space explosion is a fundamental obstacle in formal verification of designs and protocols. Several techniques for combating this problem have emerged in the past few years, among which two are significant: partialorder reductions and symbolic state space search. In asynchronous systems, interleavings of independent concurrent events are equivalent, and only a representative interleaving needs to be explored to verify local properties. Partialorder methods exploit this redundancy and visit only a subset of the reachable states. Symbolic techniques, on the other hand, capture the transition relation of a system and the set of reachable states as boolean functions. In many cases, these functions can be represented compactly using binary decision diagrams (BDDs). Traditionally, the two techniques have been practiced by two different schoolspartialorder methods with enumerative depthfirst search for the analysis of asynchronous network protocols, and symbolic bread...
H.: Static partial order reduction
 In: TACAS ’98: Proceedings of the 4th International Conference on Tools and Algorithms for Construction and Analysis of Systems
, 1998
"... Abstract. The state space explosion problem is central to automatic verification algorithms. One of the successful techniques to abate this problem is called 'partial order reduction'. It is based on the observation that in many cases the specification of concurrent programs does not depend on the o ..."
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Cited by 37 (7 self)
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Abstract. The state space explosion problem is central to automatic verification algorithms. One of the successful techniques to abate this problem is called 'partial order reduction'. It is based on the observation that in many cases the specification of concurrent programs does not depend on the order in which concurrently executed events are interleaved. In this paper we present a new version of partial order reduction that allows all of the reduction to be set up at the time of compiling the system description. Normally, partial order reduction requires developing specialized verification algorithms, which in the course of a state space search, select a subset of the possible transitions from each reached global state. In our approach, the set of atomic transitions obtained from the system description after our special compilation, already generates a smaller number of choices from each state. Thus, rather than conducting a modified search of the state space generated by the original state transition relation, our approach involves an ordinary search of the reachable state space generated by a modified state transition relation. Among the advantages of this technique over other versions of the reduction is that it can be directly implemented using existing verification tools, as it requires no change of the verification engine: the entire reduction mechanism is set up at compile time. One major application is the use of this reduction technique together with symbolic model checking and localization reduction, obtaining a combined reduction. We discuss an implementation and experimental results for SDL programs translated into COSPAN notation by applying our reduction techniques. This is part of a hardwaresoftware coverification project. 1
Using Magnetic Disk instead of Main Memory in the Mur phi Verifier
, 1998
"... In verification by explicit state enumeration a randomly accessed state table is maintained. In practice, the total main memory available for this state table is a major limiting factor in verification. We describe a version of the explicit state enumeration verifier Mur' that allows using magnet ..."
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Cited by 34 (2 self)
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In verification by explicit state enumeration a randomly accessed state table is maintained. In practice, the total main memory available for this state table is a major limiting factor in verification. We describe a version of the explicit state enumeration verifier Mur' that allows using magnetic disk instead of main memory for storing almost all of the state table. The algorithm avoids costly random accesses to disk and amortizes the cost of linearly reading the state table from disk over all states in a certain breadthfirst level. The remaining runtime overhead for accessing the disk can be strongly reduced by combining the scheme with hash compaction. We show how to do this combination efficiently and analyze the resulting algorithm. In experiments with three complex cache coherence protocols, the new algorithm achieves memory savings factors of one to two orders of magnitude with a runtime overhead of typically only around 15%. Keywords protocol verification, expli...
Partial Order Reduction in Directed Model Checking
 In 9th International SPIN Workshop on Model Checking Software, Lecture Notes in Computer Science 2318
, 2002
"... Partial order reduction is a very succesful technique for avoiding the state explosion problem that is inherent to explicit state model checking of asynchronous concurrent systems. It exploits the commutativity of concurrently executed transitions in interleaved system runs in order to reduce th ..."
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Cited by 15 (4 self)
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Partial order reduction is a very succesful technique for avoiding the state explosion problem that is inherent to explicit state model checking of asynchronous concurrent systems. It exploits the commutativity of concurrently executed transitions in interleaved system runs in order to reduce the size of the explored state space. Directed model checking on the other hand addresses the state explosion problem by using guided search techniques during state space exploration. As a consequence, shorter errors trails are found and less search effort is required than when using standard depthfirst or breadthfirst search. We analyze how to combine directed model checking with partial order reduction methods and give experimental results on how the combination of both techniques performs.
Partial order reduction for verification of timed systems
, 1999
"... conclusions or recommendations expressed in this material are those of the author and do not necessarily reflect the views of SRC, NSF, DARPA, or the United States Government. ..."
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Cited by 10 (0 self)
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conclusions or recommendations expressed in this material are those of the author and do not necessarily reflect the views of SRC, NSF, DARPA, or the United States Government.
Algorithmic Techniques in Verification by Explicit State Enumeration
, 1997
"... Modern digital systems often employ sophisticated protocols. Unfortunately, designing correct protocols is a subtle art. Even when using great care, a designer typically cannot foresee all possible interactions among the components of the system; thus, bugs like subtle race conditions or deadlocks a ..."
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Cited by 8 (4 self)
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Modern digital systems often employ sophisticated protocols. Unfortunately, designing correct protocols is a subtle art. Even when using great care, a designer typically cannot foresee all possible interactions among the components of the system; thus, bugs like subtle race conditions or deadlocks are easily overlooked. One way a computer can support the designer is by simulating random executions of the system. There is, however, a high probability of missing executions containing errors  especially in complex systems  using this simulation approach. In contrast, an automatic verifier tries to examine all states reachable from a given set of startstates. The biggest obstacle in this exhaustive approach is that often there is a very large number of reachable states. This thesis describes three techniques to increase the size of the reachable state spaces that can be handled in automatic verifiers. The techniques work in verifiers that are based on explicitly storing each reachable ...
Coalgebraic Theories of Sequences in PVS
, 1998
"... This paper explains the setting of an extensive formalisation of the theory of sequences (finite and infinite lists of elements of some data type) in the Prototype Verification System pvs. This formalisation is based on the characterisation of sequences as a final coalgebra, which is used as an axi ..."
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Cited by 8 (2 self)
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This paper explains the setting of an extensive formalisation of the theory of sequences (finite and infinite lists of elements of some data type) in the Prototype Verification System pvs. This formalisation is based on the characterisation of sequences as a final coalgebra, which is used as an axiom. The resulting theories comprise standard operations on sequences like composition (or concatenation), filtering, flattening, and their properties. They also involve the prefix ordering and proofs that sequences form an algebraic complete partial order. The finality axiom gives rise to various reasoning principles, like bisimulation, simulation, invariance, and induction for admissible predicates. Most of the proofs of equality statements are based on bisimulations, and most of the proofs of prefix order statements use simulations. Some significant aspects of these theories are described in detail. This coalgebraic formalisation of sequences is presented as a concrete example that shows t...
Verification of the MDG Components Library in HOL
, 1998
"... The MDG system is a decision diagram based verification tool, primarily designed for hardware verification. It is based on Multiway decision diagramsan extension of the traditional ROBDD approach. In this paper we describe the formal verification of the component library of the MDG system, using ..."
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Cited by 7 (6 self)
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The MDG system is a decision diagram based verification tool, primarily designed for hardware verification. It is based on Multiway decision diagramsan extension of the traditional ROBDD approach. In this paper we describe the formal verification of the component library of the MDG system, using HOL. The hardware component library, whilst relatively simple, has been a source of errors in an earlier developmental version of the MDG system. Thus verifying these aspects is of real utility towards the verification of a decision digram based verification system. This work demonstrates how machine assisted proof can be of practical utility when applied to a small focused problem.
Combining software and hardware verification techniques
 Formal Methods in System Design
"... Abstract. Combining verification methods developed separately for software and hardware is motivated by the industry’s need for a technology that would make formal verification of realistic software/hardware codesigns practical. We focus on techniques that have proved successful in each of the two ..."
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Cited by 6 (2 self)
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Abstract. Combining verification methods developed separately for software and hardware is motivated by the industry’s need for a technology that would make formal verification of realistic software/hardware codesigns practical. We focus on techniques that have proved successful in each of the two domains: BDDbased symbolic model checking for hardware verification and partial order reduction for the verification of concurrent software programs. In this paper, we first suggest a modification of partial order reduction, allowing its combination with any BDDbased verification tool, and then describe a coverification methodology developed using these techniques jointly. Our experimental results demonstrate the efficiency of this combined verification technique, and suggest that for moderate–size systems the method is ready for industrial application.