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21
Algorithmic Aspects of Symbolic Switch Network Analysis
 IEEE Trans. CAD/IC
, 1987
"... A network of switches controlled by Boolean variables can be represented as a system of Boolean equations. The solution of this system gives a symbolic description of the conducting paths in the network. Gaussian elimination provides an efficient technique for solving sparse systems of Boolean eq ..."
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Cited by 22 (6 self)
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A network of switches controlled by Boolean variables can be represented as a system of Boolean equations. The solution of this system gives a symbolic description of the conducting paths in the network. Gaussian elimination provides an efficient technique for solving sparse systems of Boolean equations. For the class of networks that arise when analyzing digital metaloxide semiconductor (MOS) circuits, a simple pivot selection rule guarantees that most s switch networks encountered in practice can be solved with O(s) operations. When represented by a directed acyclic graph, the set of Boolean formulas generated by the analysis has total size bounded by the number of operations required by the Gaussian elimination. This paper presents the mathematical basis for systems of Boolean equations, their solution by Gaussian elimination, and data structures and algorithms for representing and manipulating Boolean formulas.
Minimizing Energy Dissipation in HighSpeed Multipliers
 Proc. IEEE Symp. on Low Power Electronics and Design
, 1997
"... This paper presents a new twogatedelay implementation of the Booth encoder and partial product generator, which eliminates the unnecessary glitches associated with the Booth multiplier. In addition, a modified signed/unsigned (MSU) and modified signgenerate (MSG) algorithms, suitable especially f ..."
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Cited by 10 (0 self)
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This paper presents a new twogatedelay implementation of the Booth encoder and partial product generator, which eliminates the unnecessary glitches associated with the Booth multiplier. In addition, a modified signed/unsigned (MSU) and modified signgenerate (MSG) algorithms, suitable especially for signed/unsigned multipliers, were developed in order to reduce the compression level needed in the Wallace tree, and hence reduce the multiplier hardware. Using these features reduces the multiplier array energy dissipation by about 30 % and increases speed by about 10%. 1.
A technique to determine powerefficient, highperformance superscalar processors
 In Proceedings of the TwentyEighth Hawaii International Conference on System Sciences
, 1995
"... Processor performance advances are increasingly inhibit(ed by limitations in thermal power dissipation. Part of the problem is the lack of architectural power estimates before implementation. Although highperformance designs exist that dissipate low power, the method for finding these designs has ..."
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Cited by 7 (0 self)
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Processor performance advances are increasingly inhibit(ed by limitations in thermal power dissipation. Part of the problem is the lack of architectural power estimates before implementation. Although highperformance designs exist that dissipate low power, the method for finding these designs has bc:en through trialanderror. This paper presents systematic techniques to find lowpower, highperformance superscalar processors tailored to specific user benchmarks. The model of power is novel because it separates power into architectural and technology components. The architectural component is found via tracedriven simulation, which also produces performance estimates. An example technology model is presented that estimates the technology component, along with critical delay time and real estate usage. This model is bwed on case studies of actual designs. It is used to solve an important problem: increasing the duplication in superscalar execution units without excessive power consumption. Results are present#ed from runs using simulated annealing to maximize processor performance subject to power and area const#raints. The major contributions of this paper are the separation of architectural and technology components of dynamic power, the use of tracedriven simulation for architectural power measurement, and the use of a nearoptimal search t,o tailor a processor design to a benchmark. 1
SCALABLE TEST GENERATORS FOR HIGHSPEED DATAPATH CIRCUITS
"... This paper explores the design of efficient test sets and testpattern generators for online BIST. The target applications are highperformance, scalable datapath circuits for which fast and complete fault coverage is required. Because of the presence of carrylookahead, most existing BIST methods ..."
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Cited by 6 (1 self)
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This paper explores the design of efficient test sets and testpattern generators for online BIST. The target applications are highperformance, scalable datapath circuits for which fast and complete fault coverage is required. Because of the presence of carrylookahead, most existing BIST methods are unsuitable for these applications. Highlevel models are used to identify potential test sets for a small version of the circuit to be tested. Then a regular test set is extracted and a test generator TG is designed to meet the following goals: scalability, small test set size, full fault coverage, and very low hardware overhead. TG takes the form of a twisted ring counter with a small decoder array. We apply our technique to various datapath circuits including a carrylookahead adder, an arithmeticlogic unit, and a multiplieradder.
Path Delay Fault Testable Modified Booth Multipliers
, 1999
"... Testing of Modified Booth Multipliers (MBMs) with respect to path delay faults, is studied in this paper. Design modifications are proposed and a path selection method is suggested. The selected paths are Single Path Propagating – Hazard Free Robustly Testable (SPP HFRT) and based on their delays t ..."
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Cited by 4 (2 self)
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Testing of Modified Booth Multipliers (MBMs) with respect to path delay faults, is studied in this paper. Design modifications are proposed and a path selection method is suggested. The selected paths are Single Path Propagating – Hazard Free Robustly Testable (SPP HFRT) and based on their delays the delay along any other path of the MBM can be calculated. The number of the selected paths is impressively small compared to all paths of the multiplier. The delay and hardware overhead imposed by the modifications are respectively negligible and small. 1.
Low power dissipation in BIST schemes for modified booth multipliers
 In International Symposium on Defect and Fault Tolerance in VLSI Systems
, 1999
"... Aiming low power dissipation during testing, in this paper we present a methodology for deriving a novel BIST scheme for Modified Booth Multipliers. Reduction of the power dissipation is achieved by: (a) introducing a suitable Test Pattern Generator (TPG) built of a 4bit binary and a 4bit Gray cou ..."
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Cited by 4 (1 self)
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Aiming low power dissipation during testing, in this paper we present a methodology for deriving a novel BIST scheme for Modified Booth Multipliers. Reduction of the power dissipation is achieved by: (a) introducing a suitable Test Pattern Generator (TPG) built of a 4bit binary and a 4bit Gray counter, (b) properly assigning the TPG outputs to the multiplier inputs and (c) significantly reducing the test set length. The achieved reduction of the total power dissipation is from 44.1 % to 54.9%, the average reduction per test vector is from 21.4 % to 36.5 % while the reduction of the peaks is from 15.8 % to 34.3%, depending on the implementation of the basic cells and the size of the MBM. The test application time is also reduced by 28.9 % while the introduced BIST scheme implementation overhead is very small. 1.
VLSI Implementation of a Runtime Configurable Computing Integrated Circuit  The Stallion Chip
, 1998
"... Reconfigurable computing architectures are gaining popularity as a replacement for generalpurpose architectures for many high performance embedded applications. These machines support parallel computation and direct the data from the producers of an intermediate result to the consumers over custom p ..."
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Cited by 2 (0 self)
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Reconfigurable computing architectures are gaining popularity as a replacement for generalpurpose architectures for many high performance embedded applications. These machines support parallel computation and direct the data from the producers of an intermediate result to the consumers over custom pathways. The Wormhole Runtime Reconfigurable (RTR) computing architecture is a concept developed at Virginia Tech to address the weaknesses of contemporary FPGAs for configurable computing. The Stallion chip is a fullcustom configurable computing "FPGA"like integrated circuit with a coarse grained nature. Based on the result of the first generation device, the Colt chip, the Stallion chip is a followup configurable computing chip. This thesis focuses on the VLSI layout implementation of the Stallion chip. E#ort has been made to explain many facts and advantages of the Wormhole Configurable Computing Machine (CCM). Design techniques, strategies, circuit characterization, performance estimation, and ways to solve problems when using CAD layout design tools are illustrated.
The HIPERLAN Equalizer ASIC Complexity and its Relationship With the Training Header
"... In this document, an attempt is made to estimate the size of the HIPERLAN equalizer ASIC by extrapolating from existing adaptive equalizer ASICs and making certain assumptions regarding the process and methodology used to design the HIPERLAN equalizer. Two scenarios are considered, first, an equaliz ..."
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In this document, an attempt is made to estimate the size of the HIPERLAN equalizer ASIC by extrapolating from existing adaptive equalizer ASICs and making certain assumptions regarding the process and methodology used to design the HIPERLAN equalizer. Two scenarios are considered, first, an equalizer using the LMS algorithm every baud to update the tap coefficients and second, an equalizer using an RLS algorithm performing a set of updates every ten baud intervals. It was discovered that the computational complexity of both approaches are within the same order of magnitude, however, the LMS ASIC will occupy at most half the size of its RLS counterpart. The smaller IC will reduce the overall system cost at the expense of the longer convergence time required by the LMS algorithm. The paper also demonstrates that when the overall packet processing delay is taken into account, the slowerconverging and cheaper LMS type equalizer will actually produce faster turnaround times for short packets than its RLS counter part. Thus, a new training header length is suggested that would allow vendors some flexibility in choosing the structure that best suites their product.
Algorithms for Power Consumption Reduction and Speed Enhancement In . . .
 IN HIGHPERFORMANCE PARALLEL MULTIPLIERS, POWER AND TIMING MODELLING, OPTIMIZATION AND SIMULATION (PATMOS
, 1997
"... This paper presents a new twogatedelay implementation of the Booth encoder and partial product generator, which eliminates the unnecessary glitches associated with the Booth multiplier. In addition, a modified signed/unsigned (MSU) and modified signgenerate (MSG) algorithms, suitable especially f ..."
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Cited by 1 (0 self)
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This paper presents a new twogatedelay implementation of the Booth encoder and partial product generator, which eliminates the unnecessary glitches associated with the Booth multiplier. In addition, a modified signed/unsigned (MSU) and modified signgenerate (MSG) algorithms, suitable especially for signed/unsigned multipliers, were developed in order to reduce the compression level needed in the Wallace tree, and hence reduce the multiplier hardware. Using these features reduces the multiplier array energy dissipation by about 35% and increases speed by about 10%.