Abstract—Silicon area, performance, and testability have been, so far, the major design constraints to be met during the development of digital very-large-scale-integration (VLSI) systems. In recent years, however, things have changed; increasingly, power has been given weight comparable to the other design parameters. This is primarily due to the remarkable success of personal computing devices and wireless communication systems, which demand high-speed computations with low power consumption. In addition, there exists a strong pressure for manufacturers of high-end products to keep power under control, due to the increased costs of packaging and cooling this type of devices. Last, the need of ensuring high circuit reliability has turned out to be more stringent. The availability of tools for the automatic design of low-power VLSI systems has thus become necessary. More specifically, following a natural trend, the interests of the researchers have lately shifted to the investigation of power modeling, estimation, synthesis, and optimization techniques that account for power dissipation during the early stages of the design flow. This paper surveys representative contributions to this area that have appeared in the recent literature. Index Terms — Behavioral and logic synthesis, low power design, power management. I.

In recent years, power consumption has become a critical design concern for many VLSI systems. Nowhere is this more true than for portable, battery-operated applications, where power consumption has perhaps superceded speed and area as the overriding implementation constraint. This adds another degree of freedom - and complexity - to the design process and mandates the need for design techniques and CAD tools that address power, as well as area and speed. This thesis presents a methodology and a set of tools that support low-power system design. Low-power techniques at levels ranging from technology to architecture are presented and their relative merits are compared. Several case studies demonstrate that architecture and system-level optimizations offer the greatest opportunities for power reduction. A survey of existing power analysis tools, however, reveals a marked lack of powerconscious tools at these levels. Addressing this issue, a collection of techniques for modeling power at the register-transfer (RT) level of abstraction is described. These techniques model the impact of design complexity and signal activity on datapath, memory, control, and interconnect power consumption. Several VLSI design examples are used to verify the proposed tools, which exhibit near switch-level accuracy at RTlevel speeds. Finally, an integrated design space exploration environment is described that spans several levels of abstraction and embodies many of the power optimization and analysis strategies presented in this thesis.

The adoption of register-transfer level (RTL) sign-off in ASIC design methodologies, and the increasing scale of system-on-chip integration, are leading to unprecedented accuracy and efficiency demands on RT-level estimation tools. In this work, we focus on the deployment of a simulation-based RTL power estimation tool in a commercial design flow, and describe several enhancements that improve its efficiency and scalability for large, industrial designs. We profile the computational effort involved in RTL power estimation, and propose a suite of acceleration techniques, including (i) transformation of the enhanced RTL description (functional model with annotations for power estimation) to be more simulatorfriendly, (ii) computation vs. storage tradeoffs, and (iii) a novel variation of statistical sampling, called partitioned sampling. Our techniques result in an optimized allocation of the overall computational effort for power estimation and minimize the computational effort involved in the evaluation of power models. Extensive experimental results in the context of a commercial design flow have yielded promising results (e.g., upto 31X reduction in power estimation time with negligible loss of accuracy) on industrial designs of upto 1.25 million transistors. In addition to accurate power estimation for an entire circuit, these acceleration techniques result in superior accuracy of local power estimates for individual components or small sub-circuits, compared to conventional sampling or test-bench compaction techniques. 1