This paper presents the modeling of embedded systems with SimBed, an execution-driven simulation testbed that measures the execution behavior and power consumption of embedded applications and RTOSs by executing them on an accurate architectural model of a microcontroller with simulated real-time stimuli. We briefly describe the simulation environment and present a study that compares three RTOSs: µC/OS-II, a popular public-domain embedded real-time operating system; Echidna, a sophisticated, industrial-strength (commercial) RTOS; and NOS, a bare-bones multi-rate task scheduler reminiscent of typical “roll-your-own” RTOSs found in many commercial embedded systems. The microcontroller simulated in this study is the Motorola M-CORE processor: a low-power, 32-bit CPU core with 16-bit instructions, running at 20MHz.

CONTENTS DEDICATION . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . iii ACKNOWLEDGMENTS . . . . . . . . . . . . . . . . . . . . . . . . . . . iv LIST OF TABLES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . viii LIST OF FIGURES . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . ix SUMMARY . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . xii I INTRODUCTION . . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.1 Problem Statement . . . . . . . . . . . . . . . . . . . . . . . . . . . 1 1.2 Thesis Contributions . . . . . . . . . . . . . . . . . . . . . . . . . . 3 1.3 Thesis Organization and Roadmap . . . . . . . . . . . . . . . . . . . 5 II BACKGROUND AND PREVIOUS WORK . . . . . . . . . . . . 6 2.1 Locking Schemes . . . . . . . . . . . . . . . . . . . . . . . . . . . . . 6 2.1.1 Hardware Instructions for Locking . . . . . . . . . . . . . . . 8 2.1.2 Traditional Spin-Lock . . . . . . . . . . . . . . . . . . . . . . 1

The aggressive evolution of the semiconductor industry -- smaller process geometries, higher densities, and greater chip complexity -- has provided design engineers the means to create complex, high-performance Systems-on-a-Chip (SoC) designs. Such SoC designs typically have more than one processor and huge memory, all on the same chip. Dealing with the global onchip memory allocation/de-allocation in a dynamic yet deterministic way is an important issue for the upcoming billion transistor multiprocessor SoC designs. To achieve this, we propose a memory management hierarchy we call Two-Level Memory Management. To implement this memory management scheme -- which presents a paradigm shift in the way designers look at on-chip dynamic memory allocation -- we present a System-on-a-Chip Dynamic Memory Management Unit (SoCDMMU) for allocation of the global on-chip memory, which we refer to as Level Two memory management (Level One is the operating system management of memory allocated to a particular on-chip Processing Element). In this way, processing elements (heterogeneous or non-heterogeneous hardware or software) in an SoC can request and be granted portions of the global memory in a fast and deterministic time (for an example of a four processing element SoC, the dynamic memory allocation of the global onchip memory takes sixteen cycles per allocation/deallocation in the worst case). In this paper, we show how to modify an existing Real-Time Operating System (RTOS) to support the new proposed SoCDMMU. Our example shows a multiprocessor SoC that utilizes the SoCDMMU has 440% overall speedup of the application transition time over fully shared memory that does not utilize the SoCDMMU.

1 Work done when Paul was at UMD. The growing complexity of embedded applications and pressure on time-to-market has resulted in the increasing use of embedded real-time operating systems. Unfortunately, RTOSes can introduce a significant performance degradation. This paper presents the Real-Time Task Manager (RTM)—a processor extension that minimizes the performance drawbacks associated with RTOSes. The RTM accomplishes this by supporting, in hardware, a few of the common RTOS operations that are performance bottlenecks: task scheduling, time management, and event management. By exploiting the inherent parallelism of these operations, the RTM completes them in constant time, thereby significantly reducing RTOS overhead. It decreases both the processor time used by the RTOS and the maximum response time by an order of magnitude.

Abstract—This paper presents the modeling of embedded systems with SimBed, an execution-driven simulation testbed that measures the execution behavior and power consumption of embedded applications and RTOSs by executing them on an accurate architectural model of a microcontroller with simulated real-time stimuli. We briefly describe the simulation environment and present a study that compares three RTOSs: C/OS-II, a popular public-domain embedded real-time operating system; Echidna, a sophisticated, industrial-strength (commercial) RTOS; and NOS, a bare-bones multirate task scheduler reminiscent of typical “roll-your-own ” RTOSs found in many commercial embedded systems. The microcontroller simulated in this study is the Motorola M-CORE processor: a low-power, 32-bit CPU core with 16-bit instructions, running at 20MHz. Our simulations show what happens when RTOSs are pushed beyond their limits and they depict situations in which unexpected interrupts or unaccounted-for task invocations disrupt timing, even when the CPU is lightly loaded. In general, there appears no clear winner in timing accuracy between preemptive systems and cooperative systems. The power-consumption measurements show that RTOS overhead is a factor of two to four higher than it needs to be, compared to the energy consumption of the minimal scheduler. In addition, poorly designed idle loops can cause the system to double its energy consumption—energy that could be saved by a simple hardware sleep mechanism. Index Terms—Embedded systems, real-time operating systems (RTOS), power and energy modeling, performance modeling, Motorola M-CORE, C/OS-II, Echidna, Chimera. 1

this memory management scheme -- which presents a shift in the way designers look at on-chip dynamic memory allocation -- we present the System-on-a-Chip Dynamic Memory Management Unit (SoCDMMU) for allocation xiii of the global on-chip memory, which we refer to as Level Two memory management (Level One is the management of memory allocated to a particular on-chip Processing Element, e.g., an operating system's management of memory allocated to a particular processor). In this way, processing elements (heterogeneous or non-heterogeneous hardware or software) in an SoC can request and be granted portions of the global memory in a fast and deterministic time. A new tool is introduced to generate a custom optimized version of the SoCDMMU. Also, a real-time operating system is modified support the new proposed SoCDMMU. We show an example where shared memory multiprocessor SoC that employs the Two-Level Memory Management and utilizes the SoCDMMU has an overall average speedup in application transition time as well as normal execution time

As semiconductor prices drop and their performance improves, there is a rapid increase in the complexity of embedded applications. Embedded devices are getting smarter, which means that they are becoming more dif-ficult to develop. This has resulted in the more frequent use of several tech-niques designed to reduce their development time. One such technique is the use of embedded operating systems. Those operating systems used in real-time systems—real-time operating systems (RTOSes)—have the addi-tional burden of complying with timing constraints. Unfortunately, RTOSes can introduce a significant amount of performance degradation. The perfor-mance loss comes in the form of increased processor utilization, response time, and real-time jitter. This is a major limitation of RTOSes. This thesis presents the Real-Time Task Manager (RTM)—a processor extension intended to minimize the performance drawbacks associated with RTOSes. The RTM accomplishes this by implementing, in hardware, a few of the common RTOS operations that are performance bottlenecks: task scheduling, time management, and event management. By performing these operations in hardware, their inherent parallelism can be exploited more efficiently. Thus, the RTM is able to complete these RTOS operations in a trivial amount of time. Through extensive analysis of several realistic models of real-time sys-tems, the RTM is shown to be highly effective at minimizing RTOS perfor-mance loss. It decreases the processing time used by the RTOS by up to 90%. It decreases the maximum response time by up to 81%. And it decreases the maximum real-time jitter by up to 66%. Therefore, the RTM drastically reduces the effects of the RTOS performance bottlenecks.

Abstract System level design is considered a major approach to tackle the complexity of modern System-on-Chip designs. Embedded software within SoCs is gaining importance as it addresses the increasing need for flexible and feature-rich solutions. Therefore, integrating software design and co-simulation into a system level design flow is highly desirable. In this article, we present the software perspective within our systemlevel design flow. We address three major aspects: (1) modeling of a processor (from abstract to ISS-based), (2) porting of an RTOS, and (3) the embedded software generation including RTOS targeting. We describe these aspects based on a case study for the ARM7TDMI processor. We show processor models including a cycle-accurate ISSbased model (using SWARM), which executes the RTOS MicroC/OS-II. We demonstrate our flow with an automotive application of anti-lock breaks using one ECU and CAN-connected sensors. Our experimental results show that automatic SW generation is achievable and that SW designers can utilize the system level benefits. This allows the designer to develop applications more efficiently at the abstract system level.

System level design is one approach to tackle the complexity of designing a modern System-on-Chip. One major aspect is the capability of developing the system model irrespectable of the later occurring hardware software split, with the goal to develop both hardware and software seamlessly at the same time and to merge the traditionally separated development flows. Hardware/software co-simulation is needed for an efficiently integrated design flow. Depending on the design phase, this co-simulation can be performed at different levels of abstraction. Early in the design phase, a a very abstract simulation at the unpartitioned specification level yields fast functional results. On the other end, the cycle accurate simulation of RTL hardware and instruction set simulated software allows an accurate insight to the final system performance. This report focuses on the software perspective of a co-design/co-simulation environment. In form of a case study, we address three major tasks necessary to build an integrated embedded software design flow: modeling of a processor core (including an instruction set simulator), porting of a RTOS to the selected processor core, and the embedded software generation that includes RTOS targeting of the generated code. In particular, we have modeled a popular ARM core, the ARM7TDMI, at an abstract level, as well as on

Testing interfaces of an embedded system is important since the heterogeneous layers such as hardware, OS and application are tightly coupled. We propose the mutation operators in three respects, ‘When?’, ‘Where? ’ and ‘How? ’ in order to inject a fault into RTOS program when testing interface between RTOS and application. Injecting a fault without affecting the RTOS in run-time environment is the core of proposed mutation operators. We apply the mutation operators to interface testing during the integration of RTOS and application in the industrial programmable logic controller. 1.