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Scalable Network Architectures Using The Optical Transpose Interconnection System (OTIS)
, 1996
"... The Optical Transpose Interconnection System (OTIS) proposed in [14] makes use of freespace optical interconnects to augment an electronic system with nonlocal interconnections. In this paper, we show how these connections can be used to implement a largescale system with a given network topology ..."
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Cited by 45 (0 self)
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The Optical Transpose Interconnection System (OTIS) proposed in [14] makes use of freespace optical interconnects to augment an electronic system with nonlocal interconnections. In this paper, we show how these connections can be used to implement a largescale system with a given network topology using small copies of a similar topology. In particular, we show that, using OTIS, an N 2 node 4D mesh can be constructed from N copies of the Nnode 2D mesh, an N 2 node hypercube can be constructed from N copies of the Nnode hypercube, and an (N 2 ; ff 2 ; c=2) expander can be constructed from N copies of an (N; ff; c) expanders, all with small slowdown. We also show how this expander construction can be used to build multibutterfly networks in a scalable fashion. Finally, we demonstrate how the OTIS connections can be used to produce a bitparallel crossbar using many copies of bitserial crossbars with minimal overhead. 1 Introduction In principle, optical interconnect tec...
Basic Operations on the OTISMesh Optoelectronic Computer
 IEEE Transactions on Parallel and Distributed Systems
, 1999
"... In this paper we develop algorithms for some basic operations  broadcast, window broadcast, prefix sum, data sum, rank, shift, data accumulation, consecutive sum, adjacent sum, concentrate, distribute, generalize, sorting, random access read and write  on the OTISMesh [1] model. These operations ..."
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Cited by 31 (5 self)
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In this paper we develop algorithms for some basic operations  broadcast, window broadcast, prefix sum, data sum, rank, shift, data accumulation, consecutive sum, adjacent sum, concentrate, distribute, generalize, sorting, random access read and write  on the OTISMesh [1] model. These operations are useful in the development of efficient algorithms for numerous applications [2].
Scaling OptoelectronicVLSI Circuits into the 21st Century: A Technology Roadmap
, 1996
"... Technologies now exist for implementing dense surfacenormal optical interconnections for silicon CMOS VLSI using hybrid integration techniques. The critical factors in determining the performance of the resulting photonic chip are the yield on the transceiver device arrays, the sensitivity and powe ..."
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Cited by 28 (7 self)
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Technologies now exist for implementing dense surfacenormal optical interconnections for silicon CMOS VLSI using hybrid integration techniques. The critical factors in determining the performance of the resulting photonic chip are the yield on the transceiver device arrays, the sensitivity and power dissipation of the receiver and transmitter circuits, and the total optical power budget available. The use of GaAsAlGaAs multiplequantumwell pin diodes for onchip detection and modulation is one effective means of implementing the optoelectronic transceivers. We discuss a potential roadmap for the scaling of this hybrid optoelectronic VLSI technology as CMOS linewidths shrink and the characteristics of the hybrid optoelectronic tranceiver technology improve. An important general conclusion is that, unlike electrical interconnects, such dense optical interconnections directly to an electronic circuit will likely be able to scale in capacity to match the improved performance of futur...
BPC Permutations On The OTISMesh Optoelectronic Computer
 In Proceedings of the fourth International Conference on Massively Parallel Processing Using Optical Interconnections (MPPOI'97
, 1997
"... We show that the diameter of an N² processor 0TISMesh is 4vf  3. Two possible embedclings of an N × N mesh onto an 0TISMesh are evaluated. 0TISMesh algorithms for some commonly performed permutations  transpose, bit reversal, vector reversal, perfect shuffle, unshuffle, shuffled row ..."
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Cited by 25 (8 self)
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We show that the diameter of an N² processor 0TISMesh is 4vf  3. Two possible embedclings of an N × N mesh onto an 0TISMesh are evaluated. 0TISMesh algorithms for some commonly performed permutations  transpose, bit reversal, vector reversal, perfect shuffle, unshuffle, shuffled rowmajor, and bit shuffle  are developed. We also propose an algorithm for general BPC permutations.
Image Processing On The OTISMesh Optoelectronic Computer
 IEEE Transactions on Parallel and Distributed Systems
, 2000
"... We develop algorithms for histogramming, histogram modification, Hough transform, and image shrinking and expanding on an OTISMesh optoelectronic computer. Our algorithm for the Hough transform is based upon a mesh algorithm for the Hough transform which is also developed in this paper. This new me ..."
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Cited by 22 (2 self)
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We develop algorithms for histogramming, histogram modification, Hough transform, and image shrinking and expanding on an OTISMesh optoelectronic computer. Our algorithm for the Hough transform is based upon a mesh algorithm for the Hough transform which is also developed in this paper. This new mesh algorithm improves upon the mesh Hough transform algorithms of [4] and [14].
Matrix Multiplication On The OTISMesh Optoelectronic Computer
 In Proceedings of the sixth international conference on Massively Parallel Processing using Optical Interconnections (MPPOI’99
, 2001
"... We develop algorithms to multiply two vectors, a vector and a matrix, and two matrices on an OTISMesh optoelectronic computer. Two mappings, group row and group submesh [25], of a matrix onto an OTISMesh are considered and the relative merits of each compared. We show that our algorithms to mul ..."
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Cited by 22 (2 self)
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We develop algorithms to multiply two vectors, a vector and a matrix, and two matrices on an OTISMesh optoelectronic computer. Two mappings, group row and group submesh [25], of a matrix onto an OTISMesh are considered and the relative merits of each compared. We show that our algorithms to multiply a column and row vector use an optimal number of data moves for both the group row and group submesh mappings; our algorithm to multiply a row vector and a column vector is optimal for the group row mapping; and our algorithm to multiply a matrix by a column vector is optimal for the group row mapping.
Models and Algorithms for Optical and Optoelectronic Parallel Computers
 Proc. 1999 International Symposium on Parallel Architectures, Algorithms and Networks, IEEE Computer Society
, 2001
"... This paper briefly reviews some of the more popular parallelcomputer modelspipelined optical bus, optical transpose interconnect system (OTIS), and partitioned optical passive stars (POPS) networkthat employ optical interconnect. The interconnect topology and some simple algorithms for each ..."
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Cited by 18 (0 self)
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This paper briefly reviews some of the more popular parallelcomputer modelspipelined optical bus, optical transpose interconnect system (OTIS), and partitioned optical passive stars (POPS) networkthat employ optical interconnect. The interconnect topology and some simple algorithms for each model are also described.
BPC Permutations On The OTISHypercube Optoelectronic Computer
, 1997
"... this paper, we study the OTISHypercube architecture and obtain basic properties and basic permutation routing algorithms for this architecture. These algorithms can be used to develop efficient application programs ..."
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Cited by 14 (4 self)
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this paper, we study the OTISHypercube architecture and obtain basic properties and basic permutation routing algorithms for this architecture. These algorithms can be used to develop efficient application programs
HighSpeed CMOS Switch Designs for FreeSpace Optoelectronic MINs
 IEEE Transactions on VLSI
, 1995
"... We present the theory, experimental results, and analytical modeling of highspeed CMOS switches, with a 2D layout, suitable for the implementation of packetswitched freespace optoelectronic Multistage Interconnection Networks (MINs). These switches are fully connected, bidirectional, and scalea ..."
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Cited by 4 (3 self)
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We present the theory, experimental results, and analytical modeling of highspeed CMOS switches, with a 2D layout, suitable for the implementation of packetswitched freespace optoelectronic Multistage Interconnection Networks (MINs). These switches are fully connected, bidirectional, and scaleable. The first design is a proof of concept of the halfswitch, which is a twotoone multiplexer, and the 2D layout. The second design introduces a novel selfrouting concept, with contention detection and packet dropandresend capabilities. It uses threevalued logic, with 2.5V being the third value for a 5V power supply. Simulations show that for a 0.8 µm CMOS technology the switches can operate at speeds up to 250 Mbits/sec. Scaleddown versions of both designs have been successfully implemented in 2.0 µm CMOS. The analytical modeling of the switches show that large scale freespace optoelectronic MINs using this concept could offer close to Terabit/sec throughput capabilities and ver...
Digital Fourier optics
"... Analog Fourier optical processing systems can perform important classes of signal processing operations in parallel, but suffer from limited accuracy. Digital–optical equivalents of such systems could be built that share many features of the analog systems while allowing greater accuracy. We show th ..."
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Cited by 2 (0 self)
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Analog Fourier optical processing systems can perform important classes of signal processing operations in parallel, but suffer from limited accuracy. Digital–optical equivalents of such systems could be built that share many features of the analog systems while allowing greater accuracy. We show that the digital equivalent of any system consisting of an arbitrary number of lenses, filters, spatial light modulators, and sections of free space can be constructed. There are many possible applications for such systems as well as many alternative technologies for constructing them; this paper stresses the potential of freespace interconnected activedeviceplanebased optoelectronic architectures as a digital signal processing environment. Implementation of the activedevice planes through hybridization of optoelectronic components with silicon electronics should allow the realization of systems whose performance exceeds that of purely electronic systems. r 1996 Optical Society of America 1.