this article. Primary support for our work came from ONR URI Grant N00014-92-J-1617, ARPA Contract N0001493-C0249, NSF Grant MIP-9311980, and NSF PYI AwardMIP-8958568NSF.Additional support was provided by ICSI. IBM donated the RS/6000.

Run-time reconfiguration is a way of more fully exploiting the flexibility of reconfigurable FPGAs. The Run-Time Reconfiguration Artificial Neural Network (RRANN) uses run-time reconfiguration to increase the hardware density of FPGAs. The RRANN architecture also allows large amounts of parallelism to be used and is very scalable. RRANN divides the backpropagation algorithm into three sequentially executed stages and configures the FPGAs to execute only one stage at a time. The FPGAs are reconfigured as part of normal execution in order to change stages. Using reconfigurability in this way increases the number of hardware neurons a single Xilinx XC3090 can implement by 500%. Performance is effected by reconfiguration overhead, but this overhead becomes insignificant in large networks. This overhead is made even more insignificant with improved configuration methods. Run-time reconfiguration is a flexible realization of the time/space trade-off. The RRANN architecture has been designed ...

this paper, and can be referred to [3]. 11 The operations in the forward retrieving of an L-layer perceptron can be formulated as a forward affine transformation interleaved with a nonlinear scalar activation function: x l+1;j = f(

. One way to further exploit the reconfigurable resources of SRAM FPGAs and increase functional density is to reconfigure them during system operation. This process is referred to as Run-Time Reconfiguration (RTR). RTR is an approach to system implementation that divides an application or algorithm into time-exclusive operations that are implemented as separate configurations. The Run-Time Reconfiguration Artificial Neural Network (RRANN) is a proof-of-concept system that demonstrates the effectiveness of RTR for implementing neural networks. It implements the popular backpropagation training algorithm as three distinct time-exclusive FPGA configurations: feed-forward, backpropagation and update. System operation consists of sequencing through these three reconfigurations at run-time, one configuration at a time. RRANN has been fully implemented with Xilinx FPGAs, tested and shown to increase the functional density of a network up to 500% when compared to FPGA-based implementations tha...

This paper presents the Run-Time Reconfiguration Artificial Neural Network (RRANN). RRANN is a hardware implementation of the backpropagation algorithm that is extremely scalable and makes efficient use of FPGA resources. One key feature is RRANN's ability to exploit parallelism in all stages of the backpropagation algorithm including the stage where errors are propagated backward through the network.

. We present the requirements for a neurocomputer for spike-processing neural networks. In a simulation study we investigated the performance of available hardware and showed, that there is still a need for a specific neurocomputer dedicated to the simulation of spike-processing networks. On the basis of our simulation study and an investigation of the features of spike-processing networks we analyses the requirements for the design of dedicated hardware. An efficient hardware architecture should contain an event-list module, a sender-oriented connection module and a number of fixed-point processing units. 1 Introduction Experimental results [1] [2] together with theoretical studies [3] [4] suggest that the time structure of neuronal spike trains is relevant in neuronal signal processing. The synchronized firing of neuronal assemblies could serve as a versatile and general mechanism for feature binding, pattern segmentation and figure/ground separation. This mechanism could also be u...

Computer vision algorithms are natural candidates for high performance computing due to their inherent parallelism and intense computational demands. For example, a simple 3 x 3 convolution on a 512 x 512 gray scale image at 30 frames per second requires 67.5 million multiplications and 60 million additions to be performed in one second. Computer vision tasks can be classified into three categories based on their computational complexity andcommunication complexity: low-level, intermediate-level and high-level. Special-purpose hardware provides better performance compared to a general-purpose hardware for all the three levels of vision tasks. With recent advances in very large scale integration (VLSI) technology, an application specific integrated circuit (ASIC) can provide the best performance in terms of total execution time. However, long design cycle time, high development cost and inflexibility of a dedicated hardware deter design of ASICs. In contrast, field programmable gate arrays (FPGAs) support lower design verification time and easier design adaptability atalower cost. Hence, FPGAs with an array of reconfigurable logic blocks canbevery useful compute elements. FPGA-based custom computing machines are

As artificial neural networks (ANNs) gain popularity in a variety of application domains, it is critical that these models run fast and generate results in real time. Although a number of implementations of neural networks are available on sequential machines, most of these implementations require an inordinate amount of time to train or run ANNs, especially when the ANN models are large. One approach for speeding up the implementation of ANNs is to implement them on parallel machines. This paper surveys the area of parallel environments for the implementations of ANNs, and prescribes desired characteristics to look for in such implementations. 1 Introduction Although traditional von Neumann computing has been successful in many applications, it has not proved effective in solving a variety of important complex problems. At the same time, it has been observed that human beings solve these problems routinely in real time. Typical problems that fall into this class consist of perception...

xi 1 Introduction 1 1.1 Problem Statement : : : : : : : : : : : : : : : : : : : : : : : : : 6 1.2 The Neuron : : : : : : : : : : : : : : : : : : : : : : : : : : : : : 7 1.2.1 Biological Model : : : : : : : : : : : : : : : : : : : : : : 7 1.2.2 Computational Model : : : : : : : : : : : : : : : : : : : 9 1.3 Implementation Technologies : : : : : : : : : : : : : : : : : : : : 11 1.4 State of the Art : : : : : : : : : : : : : : : : : : : : : : : : : : : 14 1.5 Summary of Results : : : : : : : : : : : : : : : : : : : : : : : : 16 2 Implementation of Neural Models with Static Links 19 2.1 ANN Models with Static Links : : : : : : : : : : : : : : : : : : 20 2.1.1 The Hopfield Model : : : : : : : : : : : : : : : : : : : : : 21 2.1.2 The Perceptron Model : : : : : : : : : : : : : : : : : : : 23 2.1.3 The Multi-Layer Model : : : : : : : : : : : : : : : : : : : 24 2.2 Basic Computational Requirements : : : : : : : : : : : : : : : : 25 2.2.1 Search Phase Computations : : : : : : : : : : : : : : ...

Run-time reconfiguration is a way of more fully exploiting the flexibility of reconfigurable FPGAs. The Run-Time Reconfiguration Artificial Neural Network (RRANN) uses run-time reconfiguration to increase the hardware density of FPGAs. This is done by dividing the backpropagation algorithm into three sequentially executed stages and configuring the FPGAs to execute only one stage at a time. The FPGAs are reconfigured as part of normal execution in order to change stages. Using reconfigurability in this way increases the number of hardware neurons a single FPGA can implement by 500%. The RRANN architecture has been designed and built using commercially available hardware, and its performance has been measured. Introduction In many cases, reconfigurable Field Programmable Gate Arrays (FPGAs) are used as an easy way to prototype digital logic circuits and as a way to achieve inexpensive, low-volume, custom VLSI. The ease with which a designer can develop a circuit and then configure an ...