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52
Performance optimization of VLSI interconnect layout
 Integration, the VLSI Journal
, 1996
"... This paper presents a comprehensive survey of existing techniques for interconnect optimization during the VLSI physical design process, with emphasis on recent studies on interconnect design and optimization for highperformance VLSI circuit design under the deep submicron fabrication technologies. ..."
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Cited by 102 (32 self)
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This paper presents a comprehensive survey of existing techniques for interconnect optimization during the VLSI physical design process, with emphasis on recent studies on interconnect design and optimization for highperformance VLSI circuit design under the deep submicron fabrication technologies. First, we present a number of interconnect delay models and driver/gate delay models of various degrees of accuracy and efficiency which are most useful to guide the circuit design and interconnect optimization process. Then, we classify the existing work on optimization of VLSI interconnect into the following three categories and discuss the results in each category in detail: (i) topology optimization for highperformance interconnects, including the algorithms for total wire length minimization, critical path length minimization, and delay minimization; (ii) device and interconnect sizing, including techniques for efficient driver, gate, and transistor sizing, optimal wire sizing, and simultaneous topology construction, buffer insertion, buffer and wire sizing; (iii) highperfbrmance clock routing, including abstract clock net topology generation and embedding, planar clock routing, buffer and wire sizing for clock nets, nontree clock routing, and clock schedule optimization. For each method, we discuss its effectiveness, its advantages and limitations, as well as its computational efficiency. We group the related techniques according to either their optimization techniques or optimization objectives so that the reader can easily compare the quality and efficiency of different solutions.
Figures of Merit to Characterize the Importance of OnChip Inductance
 Proceedings of the IEEE/ACM Design Automation Conference
, 1998
"... A closed form solution for the output signal of a CMOS inverter driving an RLC transmission line is presented. This solution is based on the alpha power law for deep submicrometer technologies. Two figures of merit are presented that are useful for determining if a section of interconnect should be ..."
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Cited by 75 (24 self)
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A closed form solution for the output signal of a CMOS inverter driving an RLC transmission line is presented. This solution is based on the alpha power law for deep submicrometer technologies. Two figures of merit are presented that are useful for determining if a section of interconnect should be modeled as either an RLC or an RC impedance. The damping factor of a lumped RLC circuit is shown to be a useful figure of merit. The second useful figure of merit considered in this paper is the ratio of the rise time of the input signal at the driver of an interconnect line to the time of flight of the signals across the line. AS/X circuit simulations of an RLC transmission line and a five section RC P circuit based on a 0.25 m IBM CMOS technology are used to quantify and determine the relative accuracy of an RC model. One primary result of this study is evidence demonstrating that a range for the length of the interconnect exists for which inductance effects are prominent. Furthermore, it ...
Zero Skew Clock Routing With Minimum Wirelength
, 1992
"... In the design of high performance VLSI systems, minimization of clock skew is an increasingly important objective. Additionally, wirelength of clock routing trees should be minimized in order to reduce system power requirements and deformation of the clock pulse at the synchronizing elements of the ..."
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Cited by 73 (12 self)
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In the design of high performance VLSI systems, minimization of clock skew is an increasingly important objective. Additionally, wirelength of clock routing trees should be minimized in order to reduce system power requirements and deformation of the clock pulse at the synchronizing elements of the system. In this paper, we first present the DeferredMerge Embedding (DME) algorithm, which embeds any given connection topology to create a clock tree with zero skew while minimizing total wirelength. The algorithm always yields exact zero skew trees with respect to the appropriate delay model. Experimental results show an 8% to 15% wirelength reduction over previous constructions in [17] [18]. The DME algorithm may be applied to either the Elmore or linear delay model, and yields optimal total wirelength for linear delay. DME is a very fast algorithm, running in time linear in the number of synchronizing elements. We also present a unified BB+DME algorithm, which constructs a clock tree t...
Effects of Inductance on the Propagation Delay and Repeater Insertion in VLSI Circuits
, 2000
"... A closedform expression for the propagation delay of a CMOS gate driving a distributed line is introduced that is within 5 % of dynamic circuit simulations for a wide range of loads. It is shown that the error in the propagation delay if inductance is neglected and the interconnect is treated as a ..."
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Cited by 69 (16 self)
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A closedform expression for the propagation delay of a CMOS gate driving a distributed line is introduced that is within 5 % of dynamic circuit simulations for a wide range of loads. It is shown that the error in the propagation delay if inductance is neglected and the interconnect is treated as a distributed line can be over 35 % for current onchip interconnect. It is also shown that the traditional quadratic dependence of the propagation delay on the length of the interconnect for lines approaches a linear dependence as inductance effects increase. Onchip inductance is therefore expected to have a profound effect on traditional highperformance integrated circuit (IC) design methodologies. The closedform delay model is applied to the problem of repeater insertion in interconnect. Closedform solutions are presented for inserting repeaters into lines that are highly accurate with respect to numerical solutions. models can create errors of up to 30 % in the total propagation delay of a repeater system as compared to the optimal delay if inductance is considered. The error between the and models increases as the gate parasitic impedances decrease with technology scaling. Thus, the importance of inductance in highperformance very large scale integration (VLSI) design methodologies will increase as technologies scale. Index Terms—CMOS, highperformance, highspeed interconnect, propagation delay, VLSI.
Clock Distribution Networks in Synchronous Digital Integrated Circuits
 Proc. IEEE
, 2001
"... this paper, bears separate focus. The paper is organized as follows. In Section II, an overview of the operation of a synchronous system is provided. In Section III, fundamental definitions and the timing characteristics of clock skew are discussed. The timing relationships between a local data path ..."
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Cited by 56 (5 self)
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this paper, bears separate focus. The paper is organized as follows. In Section II, an overview of the operation of a synchronous system is provided. In Section III, fundamental definitions and the timing characteristics of clock skew are discussed. The timing relationships between a local data path and the clock skew of that path are described in Section IV. The interplay among the aforementioned three subsystems making up a synchronous digital system is described in Section V; particularly, how the timing characteristics of the memory and logic elements constrain the design and synthesis of clock distribution networks. Different forms of clock distribution networks, such as buffered trees and Htrees, are discussed. The automated layout and synthesis of clock distribution networks are described in Section VI. Techniques for making clock distribution networks less sensitive to process parameter variations are discussed in Section VII. Localized scheduling of the clock delays is useful in optimizing the performance of highspeed synchronous circuits. The process for determining the optimal timing characteristics of a clock distribution network is reviewed in Section VIII. The application of clock distribution networks to highspeed circuits has existed for many years. The design of the clock distribution network of certain important VLSIbased systems has been described in the literature, and some examples of these circuits are described in Section IX. In an effort to provide some insight into future and evolving areas of research relevant to highperformance clock distribution networks, some potentially important topics for future research are discussed in Section X. Finally, a summary of this paper with some concluding remarks is provided in Section XI
Clocking Design and Analysis for a 600MHz Alpha Microprocessor
, 1998
"... Design, analysis, and verification of the clock hierarchy on a 600MHz Alpha microprocessor is presented. The clock hierarchy includes a gridded global clock, gridded major clocks, and many local clocks and local conditional clocks, which together improve performance and power at the cost of verific ..."
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Cited by 50 (1 self)
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Design, analysis, and verification of the clock hierarchy on a 600MHz Alpha microprocessor is presented. The clock hierarchy includes a gridded global clock, gridded major clocks, and many local clocks and local conditional clocks, which together improve performance and power at the cost of verification complexity. Performance is increased with a windowpane arrangement of global clock drivers for lowering skew and employing local clocks for time borrowing. Power is reduced by using major clocks and local conditional clocks. Complexity is managed by partitioning the analysis depending on the type of clock. Design and characterization of global and major clocks use both an AWEsimbased computeraided design (CAD) tool and SPICE. Design verification of local clocks relies on SPICE along with a timingbased methodology CAD tool that includes datadependent coupling, datadependent gate loads, and resistance effects.
An analytical delay model for RLC interconnects
 IEEE Trans. Comput.Aided Des
, 1997
"... We develop an analytical delay model based on rst and second moments to incorporate inductance e ects into the delay estimate for interconnection lines. Delay estimates using our analytical model are within 15 % of SPICEcomputed delay across a wide range of interconnect parameter values. We also ex ..."
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Cited by 37 (4 self)
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We develop an analytical delay model based on rst and second moments to incorporate inductance e ects into the delay estimate for interconnection lines. Delay estimates using our analytical model are within 15 % of SPICEcomputed delay across a wide range of interconnect parameter values. We also extend our delay model for estimation of sourcesink delays in arbitrary interconnect trees. For the small tree topology considered, we observe improvements of at least 18 % in the accuracy of delay estimates when compared to the Elmore model (which isindependent of inductance), even though our estimates are as easy to compute as Elmore delay. The speedup of delay estimation via our analytical model is several orders of magnitude when compared to a simulation methodology such as SPICE. 1.
Equivalent Elmore Delay for RLC Trees
 Proceedings of the ACM/IEEE Design Automation Conference
, 2000
"... Abstract—Closedform solutions for the 50 % delay, rise time, overshoots, and settling time of signals in an tree are presented. These solutions have the same accuracy characteristics of the Elmore delay for trees and preserves the simplicity and recursive characteristics of the Elmore delay. Specif ..."
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Cited by 30 (8 self)
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Abstract—Closedform solutions for the 50 % delay, rise time, overshoots, and settling time of signals in an tree are presented. These solutions have the same accuracy characteristics of the Elmore delay for trees and preserves the simplicity and recursive characteristics of the Elmore delay. Specifically, the complexity of calculating the time domain responses at all the nodes of an tree is linearly proportional to the number of branches in the tree and the solutions are always stable. The closedform expressions introduced here consider all damping conditions of an circuit including the underdamped response, which is not considered by the Elmore delay due to the nonmonotone nature of the response. The continuous analytical nature of the solutions makes these expressions suitable for design methodologies and optimization techniques. Also, the solutions have significantly improved accuracy as compared to the Elmore delay for an overdamped response. The solutions introduced here for trees can be practically used for the same purposes that the Elmore delay is used for trees.
Digital Circuit Optimization via Geometric Programming
 Operations Research
, 2005
"... informs ® doi 10.1287/opre.1050.0254 © 2005 INFORMS This paper concerns a method for digital circuit optimization based on formulating the problem as a geometric program (GP) or generalized geometric program (GGP), which can be transformed to a convex optimization problem and then very efficiently s ..."
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Cited by 29 (7 self)
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informs ® doi 10.1287/opre.1050.0254 © 2005 INFORMS This paper concerns a method for digital circuit optimization based on formulating the problem as a geometric program (GP) or generalized geometric program (GGP), which can be transformed to a convex optimization problem and then very efficiently solved. We start with a basic gate scaling problem, with delay modeled as a simple resistorcapacitor (RC) time constant, and then add various layers of complexity and modeling accuracy, such as accounting for differing signal fall and rise times, and the effects of signal transition times. We then consider more complex formulations such as robust design over corners, multimode design, statistical design, and problems in which threshold and power supply voltage are also variables to be chosen. Finally, we look at the detailed design of gates and interconnect wires, again using a formulation that is compatible with GP or GGP.
A Bus Delay Reduction Technique Considering Crosstalk
 Proc. DATE
, 2000
"... As the CMOS technology scaled down, the horizontal coupling capacitance between adjacent wires plays dominant part in wire load, crosstalk interference becomes a serious problem for VLSI design. We focused on delay increase caused by crosstalk. Onchip bus delay is maximized by crosstalk effect when ..."
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Cited by 25 (1 self)
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As the CMOS technology scaled down, the horizontal coupling capacitance between adjacent wires plays dominant part in wire load, crosstalk interference becomes a serious problem for VLSI design. We focused on delay increase caused by crosstalk. Onchip bus delay is maximized by crosstalk effect when adjacent wires simultaneously switch for opposite signal transition directions. This paper proposes a bus delay reduction technique by intentional skewing signal transition timing of adjacent wires. An approximated equation of bus delay shows our delay reduction technique is effective for repeaterinserted bus. The result of SPICE simulation shows that the total bus delay reduction by from 5% to 20% can be achieved.