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151
New Algorithms for Gate Sizing: A Comparative Study
 IN DAC
, 1996
"... Gate sizing consists of choosing for each node of a mapped network a gate implementation in the library so that some cost function is optimized under some constraints. It has a significant impact on the delay, power dissipation, and area of the final circuit. This paper compares five gate sizing alg ..."
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Cited by 29 (0 self)
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Gate sizing consists of choosing for each node of a mapped network a gate implementation in the library so that some cost function is optimized under some constraints. It has a significant impact on the delay, power dissipation, and area of the final circuit. This paper compares five gate sizing algorithms targeting discrete, nonlinear, nonunimodal, constrained optimization. The goal is to overcome the nonlinearity and nonunimodality of the delay and the power to achieve good quality results within a reasonable CPU time, e.g., handling a 10000 node network in 2 hours. We compare the five algorithms on constraint free delay optimization and delay constrained power optimization, and show that one method is superior to the others.
Toward Achieving Energy Efficiency in Presence of Deep Submicron Noise
 IEEE TRANSACTIONS ON VLSI SYSTEMS
, 2000
"... Presented in this paper are 1) informationtheoretic lower bounds on energy consumption of noisy digital gates and 2) the concept of noise tolerance via coding for achieving energy efficiency in the presence of noise. In particular, lower bounds on a) circuit speed and supply voltage ; b) transition ..."
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Cited by 27 (1 self)
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Presented in this paper are 1) informationtheoretic lower bounds on energy consumption of noisy digital gates and 2) the concept of noise tolerance via coding for achieving energy efficiency in the presence of noise. In particular, lower bounds on a) circuit speed and supply voltage ; b) transition activity in presence of noise; c) dynamic energy dissipation; and d) total (dynamic and static) energy dissipation are derived. A surprising result is that in a scenario where dynamic component of power dissipation dominates, the supply voltage for minimum energy operation ( ) is greater than the minimum supply voltage ( min ) for reliable operation. We then propose noise tolerance via coding to approach the lower bounds on energy dissipation. We show that the lower bounds on energy for an offchip I/O signaling example are a factor of 24 below present day systems. A very simple Hamming code can reduce the energy consumption by a factor of 3 , while ReedMuller (RM) codes give a 4 reduction in energy dissipation.
Power Estimation in Sequential Circuits
, 1995
"... A new method for power estimation in sequential circuits is presented that is based on a statistical estimation technique. By applying randomly generated input sequences to the circuit, statistics on the latch outputs are collected, by simulation, that allow efficient power estimation for the whole ..."
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Cited by 27 (5 self)
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A new method for power estimation in sequential circuits is presented that is based on a statistical estimation technique. By applying randomly generated input sequences to the circuit, statistics on the latch outputs are collected, by simulation, that allow efficient power estimation for the whole design. An important advantage of this approach is that the desired accuracy can be specified upfront by the user; the algorithm iterates until the specified accuracy is achieved. This has been implemented and tested on a number of sequential circuits and found to be much faster than existing techniques. We can complete the analysis of a circuit with 1,452 flipflops and 19,253 gates in about 4.6 hours (the largest test case reported previously has 223 flipflops). I. INTRODUCTION The dramatic decrease in feature size and the corresponding increase in the number of devices on a chip, combined with the growing demand for portable communication and computing systems, have made power consump...
SystemLevel PowerAware Design Techniques in RealTime Systems
 Proceedings of the IEEE
, 2003
"... Power and energy consumption has recently become an important issue and consequently, poweraware techniques are being devised at all levels of system design; from the circuit and device level, to the architectural, compiler, operating system and networking layers. In this survey we concentrate on p ..."
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Cited by 26 (0 self)
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Power and energy consumption has recently become an important issue and consequently, poweraware techniques are being devised at all levels of system design; from the circuit and device level, to the architectural, compiler, operating system and networking layers. In this survey we concentrate on poweraware design techniques for realtime systems. While the main focus is on hard realtime, soft realtime systems are considered as well. We start with the motivation for focusing on these systems and provide a brief discussion on power and energy objectives. We then follow with a survey of current research on a layer by layer basis. We conclude with illustrative examples and open research challenges. This work provides an overview of poweraware techniques for the realtime system engineer as well as an uptodate reference list for the researcher.
Reducing Power Consumption of the Issue Logic
 In Workshop on ComplexityEffective Design
, 2000
"... A technique to reduce the power consumption of the issue logic of superscalar processors is presented. We have evaluated the power consumption of different parts of the architecture through a detailed cyclebycycle simulation. The results show that one of the principal power consumption's factor in ..."
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Cited by 25 (0 self)
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A technique to reduce the power consumption of the issue logic of superscalar processors is presented. We have evaluated the power consumption of different parts of the architecture through a detailed cyclebycycle simulation. The results show that one of the principal power consumption's factor in a superscalar processor is the hardware devoted to extract parallelism from applications. We propose a technique to dynamically resize the instruction queue based on the existing parallelism in different periods of the execution. With the proposed method we can save about 15 per cent on the total power consumption in the processor. 1
A Mathematical Basis For PowerReduction In Digital VLSI Systems
 IEEE Trans. Circuits Syst. II
, 1997
"... Presented in this paper is a mathematical basis for powerreduction in VLSI systems. This basis is employed to 1.) derive lower bounds on the power dissipation in digital systems and 2.) unify existing powerreduction techniques under a common framework. The proposed basis is derived from informatio ..."
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Cited by 24 (15 self)
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Presented in this paper is a mathematical basis for powerreduction in VLSI systems. This basis is employed to 1.) derive lower bounds on the power dissipation in digital systems and 2.) unify existing powerreduction techniques under a common framework. The proposed basis is derived from informationtheoretic arguments. In particular, a digital signal processing algorithm is viewed as a process of information transfer with an inherent information transfer rate requirement of R bits/sec. Architectures implementing a given algorithm are equivalent to communication networks each with a certain capacity C (also in bits/sec). The absolute lower bound on the power dissipation for any given architecture is then obtained by minimizing the signal power such that its channel capacity C is equal to the desired information transfer rate R. By including various implementation constraints, increasingly realistic lower bounds are calculated. The usefulness of the proposed theory is demonstrated via...
A detailed power model for fieldprogrammable gate arrays
 Design Automation of Electronic Systems (TODAES
, 2005
"... Power has become a critical issue for FPGA vendors. Understanding the power dissipation within FPGAs is the first step to develop powerefficient architectures and CAD tools for FPGAs. This paper describes a detailed and flexible power model which has been integrated in the widelyused Versatile Pla ..."
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Cited by 22 (5 self)
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Power has become a critical issue for FPGA vendors. Understanding the power dissipation within FPGAs is the first step to develop powerefficient architectures and CAD tools for FPGAs. This paper describes a detailed and flexible power model which has been integrated in the widelyused Versatile Place and Route (VPR) CAD tool. This power model estimates the dynamic, shortcircuit, and leakage power consumed by FPGAs. It is the first flexible power model developed to evaluate architectural tradeoffs and the efficiency of poweraware CAD tools for a variety of FPGA architectures, and is freely available for noncommercial use. The model is flexible, in that it can estimate the power for a wide variety of FPGA architectures, and it is fast, in that it does not require extensive simulation, meaning it can be used to explore a large architectural space. We show how the model can be used to investigate the impact of various architectural parameters on the energy consumed by the FPGA, focusing on the segment length, switch block topology, lookuptable size, and cluster size.
Accurate Power Estimation for Large Sequential Circuits
 IEEE International Conference on ComputerAided Design
, 1997
"... A power estimation approach is presented in which blocks of consecutive vectors are selected at random from a usersupplied realistic input vector set and the circuit is simulated for each block starting from an unknown state. This leads to two (upper and lower) bounds on the desired power value whi ..."
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Cited by 22 (2 self)
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A power estimation approach is presented in which blocks of consecutive vectors are selected at random from a usersupplied realistic input vector set and the circuit is simulated for each block starting from an unknown state. This leads to two (upper and lower) bounds on the desired power value which can be quite tight (under 10% di#erence between the two in many cases). As a result, the power dissipation is obtained by simulating only a fraction of the potentially very large vector set. 1. Introduction Power dissipation of VLSI circuits is a major concern of the semiconductor industry. Excessive power dissipation in integrated circuits causes overheating, which can lead to soft errors or permanent damage. It also limits battery life in portable equipment. Thus, there is a need to accurately estimate the power dissipation of an IC during the design phase. Several approaches have been proposed for power estimation [1], especially for estimation at the gatelevel. However, even at the...
Power Modeling for High Level Power Estimation
 IEEE Transactions on Very Large Scale Integration (VLSI) Systems
, 2000
"... In this paper, we propose a modeling approach that captures the dependence of the power dissipation of a combinational logic circuit on its input/output signal switching statistics. The resulting power macromodel, consisting of a single fourdimensional table, can be used to estimate the power consu ..."
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Cited by 21 (1 self)
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In this paper, we propose a modeling approach that captures the dependence of the power dissipation of a combinational logic circuit on its input/output signal switching statistics. The resulting power macromodel, consisting of a single fourdimensional table, can be used to estimate the power consumed in the circuit for any given input/output signal statistics. Given a lowlevel (typically gatelevel) description of the circuit, we describe a characterization process by which such a table model can be automatically built. The four dimensions of our tablebased model are the average input signal probability, average input transition density, average spatial correlation coe#cient and average output zerodelay transition density. This approach has been implemented and models have been built for many benchmark circuits. Over a wide range of input signal statistics, we show that this model gives very good accuracy, with an RMS error of about 4% and average error of about 6%. Except for one...