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58
Boolean analysis of MOS circuits
 IEEE Transactions on Computeraided Design
, 1987
"... The switchlevel model represents a digital metaloxide semiconductor (MOS) circuit as a network of charge storage nodes connected by resistive transistor switches. The functionality of such a network can be expressed as a series of systems of Boolean equations. Solving these equations symbolically ..."
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Cited by 63 (14 self)
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The switchlevel model represents a digital metaloxide semiconductor (MOS) circuit as a network of charge storage nodes connected by resistive transistor switches. The functionality of such a network can be expressed as a series of systems of Boolean equations. Solving these equations symbolically yields a set of Boolean formulas that describe the mapping from input and current state to the new network state. This analysis supports the same class of networks as the switchlevel simulator MOSSIM II and provides the same functionality, including the handling of bidirectional e ects and indeterminate (X) logic values. In the worst case, the analysis of an n node network can yield a set of formulas containing a total of O(n 3) operations. However, all but a limited set of dense, passtransistor networks give formulas with O(n) total operations. The analysis can serve as the basis of e cient programs for a variety oflogic design tasks, including: logic simulation (on both conventional and special purpose computers), fault simulation, test generation, and symbolic veri cation.
Optimizing TwoPhase, LevelClocked Circuitry (Extended Abstract)
"... We investigate two strategies for reducing the clock period of a twophase, levelclocked circuit: clock tuning, which adjusts the waveforms that clock the circuit, and retiming, which relocates circuit latches. These methods can be used to convert a circuit with edgetriggered latches into a faster ..."
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Cited by 55 (16 self)
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We investigate two strategies for reducing the clock period of a twophase, levelclocked circuit: clock tuning, which adjusts the waveforms that clock the circuit, and retiming, which relocates circuit latches. These methods can be used to convert a circuit with edgetriggered latches into a faster levelclocked one. We model a twophase circuit as a graph whose vertex set V is a collection of combinational logic blocks, and whose edge set E is a set of interconnections. Each interconnection passes through 0 or more latches, where each latch is clocked by one of two periodic, nonoverlapping waveforms, or phases. We give efficient polynomialtime algorithms for problems involving the timing verification and optimization of twophase circuitry. Included are algorithms for ffl verifyi...
Estimation of Power Dissipation in CMOS Combinational Circuits Using Boolean Function Manipulation
, 1992
"... Estimating maximum power dissipation for a CMOS logic network is difficult because the power dissipated by the network is typically a strong function of the network's inputs. This implies that the number of simulations which must be performed in order to find the maximum power dissipation is exponen ..."
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Cited by 50 (0 self)
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Estimating maximum power dissipation for a CMOS logic network is difficult because the power dissipated by the network is typically a strong function of the network's inputs. This implies that the number of simulations which must be performed in order to find the maximum power dissipation is exponential in the number of inputs to the network. In this paper we show that a simplified model of power dissipation relates maximizing dissipation to maximizing gate output activity, appropriately weighted to account for differing load capacitances. To find the input or input sequence that maximizes the weighted activity, we give algorithms for transforming the problem to a weighted rnaxsatisfiability problem, and then present exact and approximate algorithms for solving weighted maxsatisfiability. Algorithms for constructing the maxsatisfiability problem for both dynamic and static CMOS, where for the latter dissipation caused by glitching is considered, are presented. Also, we present efficient exact and approximate methods for solving weighted maxsatlsfiability and show that these methods are viable for largescale problems through examination of experimental results.
Integrating Projections
 IN
, 1998
"... This paper describes three techniques for reachability analysis for systems modeled by ordinary differential equations (ODEs). First, linear models with regions modeled by convex polyhedra are considered, and an exact algorithm is presented. Next, nonconvex polyhedra are considered, and techniq ..."
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Cited by 38 (5 self)
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This paper describes three techniques for reachability analysis for systems modeled by ordinary differential equations (ODEs). First, linear models with regions modeled by convex polyhedra are considered, and an exact algorithm is presented. Next, nonconvex polyhedra are considered, and techniques are presented for representing a polyhedron by its projection onto twodimensional subspaces. This approach yields a compact representation, and allows efficient algorithms from computational geometry to be employed. Within this context, an approximation technique for reducing nonlinear ODE models to linear nonhomogeneous models is presented. This
A Methodology for Hardware Verification Based on Logic Simulation
 Journal of the ACM
, 1991
"... A logic simulator can prove the correctness of a digital circuit if it can be shown that only circuits fulfilling the system specification will produce a particular response to a sequence of simulation commands. This style of verification has advantages over other proof methods in being readily a ..."
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Cited by 37 (5 self)
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A logic simulator can prove the correctness of a digital circuit if it can be shown that only circuits fulfilling the system specification will produce a particular response to a sequence of simulation commands. This style of verification has advantages over other proof methods in being readily automated and requiring less attention on the part of the user to the lowlevel details of the design. It has advantages over other approaches to simulation in providing more reliable results, often at a comparable cost.
A Highspeed DES Implementation for Network Applications
, 1992
"... This paper describes a highspeed data encryption chip implementing the Data Encryption Standard (DES). The DES implementation supports Electronic Code Book mode and Cipher Block Chaining mode. The chip is based on a gallium arsenide (GaAs) gate array containing 50K transistors. At a clock frequency ..."
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Cited by 34 (0 self)
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This paper describes a highspeed data encryption chip implementing the Data Encryption Standard (DES). The DES implementation supports Electronic Code Book mode and Cipher Block Chaining mode. The chip is based on a gallium arsenide (GaAs) gate array containing 50K transistors. At a clock frequency of 250 MHz, data can be encrypted or decrypted at a rate of 1 GBit/second, making this the fastest singlechip implementation reported to date. High performance and high density have been achieved by using customdesigned circuits to implement the core of the DES algorithm. These circuits employ precharged logic, a methodology novel to the design of GaAs devices. A pipelined flowthrough architecture and an efficient key exchange mechanism make this chip suitable for lowlatency network controllers. iv Contents 1 Introduction 1 2 DES Algorithm 1 3 GaAs Gate Array 4 4 DES Chip Implementation 6 4.1 Organization : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : : :...
Techniques for the Power Estimation of Sequential Logic Circuits Under UserSpecified Input Sequences and Programs
 IEEE Transactions on VLSI Systems
, 1994
"... We describe an approach to estimate the average power dissipation in sequential logic circuits under userspecified input sequences or programs. This approach will aid the design of programmable controllers or processors, by enabling the estimation of the power dissipated when the controller or proc ..."
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Cited by 34 (8 self)
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We describe an approach to estimate the average power dissipation in sequential logic circuits under userspecified input sequences or programs. This approach will aid the design of programmable controllers or processors, by enabling the estimation of the power dissipated when the controller or processor is running specific application programs. Current approaches to sequential circuit power estimation are limited by the fact that the input sequences to the sequential circuit are assumed to be uncorrelated. In reality, the inputs come from other sequential circuits, or are application programs. In this paper we show how userspecified sequences and programs can be modeled using a finite state machine, termed an inputmodeling finite state machines or IMFSM. Power estimation can be carried out using existing sequential circuit power estimation methods on a cascade circuit consisting of the IMFSM and the original sequential circuit. I. INTRODUCTION Average power dissipation estimation is...
Harmony: Static Noise Analysis of Deep Submicron Digital Integrated Circuits
 IEEE Trans. CAD
, 1999
"... As technology scales into the deep submicron regime, noise immunity is becoming a metric of comparable importance to area, timing, and power for the analysis and design of very large scale integrated (VLSI) systems. A metric for noise immunity is defined, and a static noise analysis methodology base ..."
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Cited by 27 (5 self)
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As technology scales into the deep submicron regime, noise immunity is becoming a metric of comparable importance to area, timing, and power for the analysis and design of very large scale integrated (VLSI) systems. A metric for noise immunity is defined, and a static noise analysis methodology based on this noisestability metric is introduced to demonstrate how noise can be analyzed systematically on a fullchip basis using simulationbased transistorlevel analysis. We then describe Harmony, a twolevel (macro and global) hierarchical implementation of static noise analysis. At the macro level, simplified interconnect models and timing assumptions guide efficient analysis. The global level involves a careful combination of static noise analysis, static timing analysis, and detailed interconnect macromodels based on reducedorder modeling techniques. We describe how the interconnect macromodels are practically employed to perform coupling analysis and how timing constraints can be use...
A CMOS Area Image Sensor With Pixel Level A/D Conversion
 IN ISSCC DIGEST OF TECHNICAL PAPERS
, 1995
"... A CMOS 64 x 64 pixel area image sensor chip using SigmaDelta modulation at each pixel for A/D conversion is described. The image data output is digital. The chip was fabricated using a 1.2µm two layer metal single layer poly nwell CMOS process. Each pixel block consists of a phototransistor and ..."
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Cited by 26 (7 self)
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A CMOS 64 x 64 pixel area image sensor chip using SigmaDelta modulation at each pixel for A/D conversion is described. The image data output is digital. The chip was fabricated using a 1.2µm two layer metal single layer poly nwell CMOS process. Each pixel block consists of a phototransistor and 22 MOS transistors. Test results demonstrate a dynamic range potentially greater than 93dB, a signal to noise ratio (SNR) of up to 61dB, and dissipation of less than 1mW with a 5V power supply.