Technology trends and especially portable applications drive the quest for low-power VLSI design. Solutions that involve algorithmic, structural or physical transformations are sought. The focus is on developing low power circuits without affecting too much the performance (area, latency, period). For CMOS circuits most power is dissipated as dynamic power for charging and discharging node capacitances. This is why many promising results in lowpower design are obtained by minimizing the number of transitions inside the CMOS circuit. While it is generally accepted that because of the large capacitances involved much of the power dissipated by an IC is at the I/O little has been specifically done for decreasing the I/O power dissipation. We propose the Bus-Invert method of coding the I/O which lowers the bus activity and thus decreases the I/O peak power dissipation by 50% and the I/O average power dissipation by up to 25%. The method is general but applies best for dealing with buses. T...

Low supply voltage requires the device threshold to be reduced in order to maintain performance. Due to the exponential relationship between leakage current and threshold voltage in the weak inversion region, leakage power can no longer be ignored. In this paper we present a technique to accurately estimate leakage power by accurately modeling the leakage current in transistor stacks. The standby leakage current model has been veri ed by HSPICE. We demonstrate that the dependence of leakage power on primary input combinations can be accounted for by this model. Based on our analysis we can determine good bounds for leakage power in the standby mode. As a by-product of this analysis, we can also determine the set of input vectors which can put the circuits in the low-power standby mode. Results on a large number of benchmarks indicate that proper input selection can reduce the standby leakage power by more than 50 % for some circuits.

: Excessive power supply and ground currents in integrated circuits can severely affect circuit reliability and performance. Some of the problems arising from excessive current flow are : (1) excessive voltage drop (glitches) on the power/ground lines, which can lead to soft errors, and (2) large instantaneous power dissipation, which causes overheating and ultimately leads to performance degradation. Maximum current estimates are, therefore, needed in the supply lines in order to determine the severity of these problems. These currents, however, depend on the specific input patterns that are applied to the circuit. Most previous work in this area has focused on search techniques that attempt to locate the worst case current by searching for the corresponding worst case input patterns. However, since the input space is huge, search-based algorithm for this problem can take an exponential amount of time, in the worst case. In this paper, we propose a pattern-independent, linear-time alg...

In recent years, power consumption has become a critical design concern for many VLSI systems. Nowhere is this more true than for portable, battery-operated applications, where power consumption has perhaps superceded speed and area as the overriding implementation constraint. This adds another degree of freedom - and complexity - to the design process and mandates the need for design techniques and CAD tools that address power, as well as area and speed. This thesis presents a methodology and a set of tools that support low-power system design. Low-power techniques at levels ranging from technology to architecture are presented and their relative merits are compared. Several case studies demonstrate that architecture and system-level optimizations offer the greatest opportunities for power reduction. A survey of existing power analysis tools, however, reveals a marked lack of powerconscious tools at these levels. Addressing this issue, a collection of techniques for modeling power at the register-transfer (RT) level of abstraction is described. These techniques model the impact of design complexity and signal activity on datapath, memory, control, and interconnect power consumption. Several VLSI design examples are used to verify the proposed tools, which exhibit near switch-level accuracy at RTlevel speeds. Finally, an integrated design space exploration environment is described that spans several levels of abstraction and embodies many of the power optimization and analysis strategies presented in this thesis.

We address the problem of estimating the average switching activity of combinational circuits under random input sequences. Switching activity is strongly affected by gate delays, and for this reason we use a variable delay model in estimating switching activity. Unlike most probabilistic methods that estimate switching activity, our method takes into account correlation caused at internal gates in the circuit due to reconvergence of input signals.

We present a genetic-algorithm-based approach for estimating the maximum power dissipation and instantaneous current through supply lines for CMOS circuits. Our approach can handle large combinational and sequential circuits with arbitrary but known delays. To obtain accurate results we extract the timing and current information from transistor-level and general-delay gate-level simulation. Our experimental results show that the patterns generated by our approach produce on the average a lower bound on the maximum power which is 41 % tighter than the one obtained by weighted random patterns for estimating the maximum power. Also, our lower bound for the maximum instantaneous current is 21 % tighter as compared to the weighted random patterns. 1.