Recently, various multibit noise-shaping digital-toanalog converters (DAC's) have been proposed that use digital signal processing techniques to cause the DAC noise arising from analog component mismatches to be spectrally shaped. Such DAC's have the potential to significantly increase the present precision limits of 16 data converters by eliminating the need for one-bit quantization in delta-sigma modulators. This paper extends the practicality of the noise-shaping DAC approach by presenting a general noise-shaping DAC architecture along with two special-case configurations that achieve first- and second-order noise-shaping, respectively. The second-order DAC configuration, in particular, is the least complex of those currently known to the author. Additionally, the paper provides a rigorous explanation of the apparent paradox of how the DAC noise can be spectrally shaped even though the sources of the DAC noise---the errors introduced by the analog circuitry---are not known to the ...

This paper presents a second-order ## modulator for audio-band A#D conversion implemented in a 3.3V, 0.5#m, single-poly CMOS process using metal-metal capacitors that achieves 98dB peak SINAD and 105dB peak SFDR. The design uses a low-complexity #rst-order mismatch-shaping 33-level DAC and a 33-level #ash ADC with digital common-mode rejection and dynamic element matching of comparator o#sets. These signal processing innovations, combined with established circuit techniques, enable state of the art performance in CMOS technology optimized for digital circuits. I. Introduction For mixed-signal ICs with high digital circuit content, single-poly CMOS optimized for digital circuits can provide the lowest overall implementation cost. For example, it is preferable to avoid the expense of double-poly capacitors, thick-oxide transistors for 5V operation, or other analog process enhancements when analog circuits such as data converters make up only a small portion of the total die area. This ...

This paper describes a background calibration method for enhancing the accuracy and linearity of a switched-capacitor digital-to-analog converter. It can be used alone or in combination with mismatch shaping to achieve very high accuracy and linearity combined with high speed. 1.

A second-order audio analog-to-digital converter (ADC) 16 modulator using a second-order 33-level tree-structured mismatch-shaping digital-to-analog converter (DAC) is presented. Key logic simplifications in the design of the mismatch -shaping DAC encoder are shown which yield the lowest complexity second-order mismatch-shaping DAC known to the authors. The phenomenon of signal-dependent DAC noise modulation in mismatch-shaping DACs is illustrated, and a modified second-order input-layer switching block is presented which reduces inband DAC noise modulation by 6 dB. Implementation details and measured performance of the 3.3-V 0.5- m single-poly CMOS prototype are presented. All 12 prototype devices achieve better than 100-dB signal-to-noise-and-distortion and 102-dB dynamic range over a 10--20 kHz measurement bandwidth. Index Terms---analog--digital conversion, CMOS analog integrated circuits, delta--sigma modulation, digital--analog conversion, dynamic element matching, mixed analog--digital integrated circuits. I.

Mismatch-shaping digital-to-analog converters (DACs) have become widely used in high-performance delta-sigma data converters because they facilitate delta-sigma modulators with multibit quantization. Relative to single-bit quantization, multibit quantization significantly relaxes the analog circuit performance necessary to achieve a given level of data converter precision, but significant digital logic is required to perform the mismatch shaping. In modern very large scale integration processes optimized for digital circuitry, this tends to be a good tradeoff in terms of both area and power consumption. It is nonetheless desirable to minimize the digital complexity as much as possible. Moreover, in delta--sigma analog-to-digital converters the mismatch-shaping logic is in the feedback path of the delta-sigma modulator, so it is essential to maintain a sufficiently small propagation delay through the mismatch-shaping logic. This paper presents and analyzes several variations of the switching blocks within a tree-structured mismatch-shaping DAC that result in the most hardware-efficient first-order and second-order mismatch -shaping DAC implementations yet known to the authors. The variations presented allow designers to tradeoff complexity for propagation-delay reduction so as to tailor designs to specific applications.

High-performance analog-to-digital converters, digital-to-analog converters, and fractional- frequency synthesizers based on delta--sigma (16) modulation---collectively referred to as data converters---have contributed significantly to the high level of integration seen in recent commercial wireless handset transceivers. This paper presents a tutorial on data converters and their uses and implications with respect to wireless transceiver architectures.

Abstract—Many applications employ digital-to-analog converters (DACs) to obtain the advantages of digital processing (e.g., low power and physical size, resilience to noise, etc.) to generate signals, such as voltages, that are analog in nature. Given the appropriate numerical representation of its input, the DAC ideally behaves as a linear gain element. However, as a result of inevitable component mismatches, the output of a multibit DAC (i.e., a DAC designed to output more than two analog levels) is a nonlinear function of its input. The resulting distortion, called DAC noise, limits the overall signal-to-noise ratio (SNR) and hence the obtainable accuracy of the DAC. Mismatch-shaping DACs exploit built-in redundancy to suppress the DAC noise in the input signal’s frequency band. Although mismatch-shaping DACs are widely used in commercial products, little theory regarding the structure of their DAC noise has been published to date. Consequently, designers have been forced to rely upon simulations to estimate DAC noise power and behavior, which can be misleading because the DAC noise depends on the DAC input. This paper addresses this problem. It presents an analysis of the DAC noise power spectral density (PSD) in a commonly used mismatch-shaping DAC: the dithered first-order low-pass tree-structured DAC. This design ensures that its DAC noise has a spectral null at dc (i.e., zero frequency) by generating digital, dc-free sequences using the same techniques that have been developed for line codes. An expression is derived for the DAC noise PSD that depends on the statistics of these sequences and is used to show various properties of the DAC noise. Specifically, an attainable bound is derived for the signal-band DAC noise power that can be used to predict worst case performance in practical circuits. Index Terms—Analog-to-digital, data converters, dc-free sequences, delta–sigma (16), digital-to-analog, dynamic element matching, mismatch shaping, multibit, sigma–delta, spectral shaping. I.

Abstract not found

endorsement of any of the University of Pennsylvania's products or services. Internal or personal use of this material is permitted. However, permission to reprint/republish this material for advertising or promotional purposes or for creating new collective works for resale or redistribution must be obtained from the IEEE by writing to pubs-permissions@ieee.org. By choosing to view this document, you agree to all provisions of the copyright laws protecting it. This paper is posted at ScholarlyCommons.