This paper was the last in a series about the retargetable peephole optimizer PO, and it was the only one to appear in a PLDI/CC conference. PO is perhaps best known for its influence on GCC [Stallman], a compiler with many targets and wide use. Peephole optimizers [McKeeman 1965] scan object code for instruction sequences that can be replaced profitably with better sequences. For example, the source code i = j; if (i> 0) … might compile into move j,i test i bne L1 On machines that set the condition codes or flags as a side effect of the move, the test is redundant. Even if the code generated for the source statements is flawless in isolation, the optimal

Many high-end DSP processors employ both multiple memory banks and heterogeneous register files to improve performance and power consumption. The complexity of such architectures presents a great challenge to compiler design. In this article, we present an approach for variable partitioning and instruction scheduling to maximally exploit the benefits provided by such architectures. Our approach is built on a novel graph model which strives to capture both performance and power demands. We propose an algorithm to iteratively find the variable partition such that the maximum energy saving is achieved while satisfying the given performance constraint. Experimental results demonstrate the effectiveness of our approach. Categories and Subject Descriptors: D.3.4 [Programming Languages]: Processors—Compilers;C.3[Special-Purpose and Application-Based Systems]—Signal processing systems;B.5.1 [Register-Transfer-Level Implementation]: Design—Memory design