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39
The NPcompleteness column: an ongoing guide
 Journal of Algorithms
, 1985
"... This is the nineteenth edition of a (usually) quarterly column that covers new developments in the theory of NPcompleteness. The presentation is modeled on that used by M. R. Garey and myself in our book ‘‘Computers and Intractability: A Guide to the Theory of NPCompleteness,’ ’ W. H. Freeman & Co ..."
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Cited by 188 (0 self)
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This is the nineteenth edition of a (usually) quarterly column that covers new developments in the theory of NPcompleteness. The presentation is modeled on that used by M. R. Garey and myself in our book ‘‘Computers and Intractability: A Guide to the Theory of NPCompleteness,’ ’ W. H. Freeman & Co., New York, 1979 (hereinafter referred to as ‘‘[G&J]’’; previous columns will be referred to by their dates). A background equivalent to that provided by [G&J] is assumed, and, when appropriate, crossreferences will be given to that book and the list of problems (NPcomplete and harder) presented there. Readers who have results they would like mentioned (NPhardness, PSPACEhardness, polynomialtimesolvability, etc.) or open problems they would like publicized, should
Algorithms and Complexity Concerning the Preemptive Scheduling of Periodic, RealTime Tasks on One Processor
 RealTime Systems
, 1990
"... We investigate the preemptive scheduling of periodic, realtime task systems on one processor. First, we show that when all parameters to the system are integers, we may assume without loss of generality that all preemptions occur at integer time values. We then assume, for the remainder of the pape ..."
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Cited by 179 (13 self)
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We investigate the preemptive scheduling of periodic, realtime task systems on one processor. First, we show that when all parameters to the system are integers, we may assume without loss of generality that all preemptions occur at integer time values. We then assume, for the remainder of the paper, that all parameters are indeed integers. We then give as our main lemma both necessary and sufficient conditions for a task system to be feasible on one processor. Although these conditions cannot, in general, be tested efficiently (unless P = NP), they do allow us to give efficient algorithms for deciding feasibility on one processor for certain types of periodic task systems. For example, we give a pseudopolynomial time algorithm for synchronous systems whose densities are bounded by a fixed constant less than 1. This algorithm represents an exponential improvement over the previous best algorithm. We also give a polynomialtime algorithm for systems having a fixed number of distinct typ...
TGFF: Task Graphs for Free
, 1998
"... We present a usercontrollable, generalpurpose, pseudorandom task graph generator called Task Graphs For Free (TGFF). TGFF creates problem instances for use in allocation and scheduling research. It has the ability to generate independent tasks as well as task sets which are composed of partially o ..."
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Cited by 138 (14 self)
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We present a usercontrollable, generalpurpose, pseudorandom task graph generator called Task Graphs For Free (TGFF). TGFF creates problem instances for use in allocation and scheduling research. It has the ability to generate independent tasks as well as task sets which are composed of partially ordered task graphs. A complete description of a scheduling problem instance is created, including attributes for processors, communication resources, tasks, and intertask communication. The user may parametrically control the correlations between attributes. Sharing TGFF's parameter settings allows researchers to easily reproduce the examples used by others, regardless of the platform on which TGFF is run.
Preemptively Scheduling HardRealTime Sporadic Tasks on One Processor
 In Proceedings of the 11th RealTime Systems Symposium
, 1990
"... In this paper, we consider the preemptivescheduling of hardrealtime sporadic task systems on one processor. Wefirstgive necessary and sufficient conditions for a sporadic task system to be feasible (i.e., schedulable). The conditions cannot, in general, be tested efficiently (unless P = NP). They ..."
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Cited by 130 (25 self)
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In this paper, we consider the preemptivescheduling of hardrealtime sporadic task systems on one processor. Wefirstgive necessary and sufficient conditions for a sporadic task system to be feasible (i.e., schedulable). The conditions cannot, in general, be tested efficiently (unless P = NP). They do, however, lead to a feasibilitytestthat runs in efficient pseudopolynomial time for a very large percentage of sporadic task systems. 1 Introduction Scheduling theory as it applies to hardrealtime environments  environments where the missing of a single deadline may have disastrous consequences  seems to currently be enjoying a renaissance. Hardreal time scheduling problems may concern either fixedduration tasks or recurring tasks that must be completed within a certain time frame. The problems most studied within the recurring category involve periodically recurring tasks [LL73, LM80, LM81, LW82,Mok83, BHR90]. Aperiodically or sporadically recurring tasks have also been stud...
Scheduling algorithms and operating systems support for realtime systems
 PROCEEDINGS OF THE IEEE
, 1994
"... This paper summarizes the state of the realtime field in the areas of scheduling and operating system kernels. Given the vast amount of work that has been done by both the operations research and computer science communities in the scheduling area, we discuss four paradigms underlying the schedulin ..."
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Cited by 115 (1 self)
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This paper summarizes the state of the realtime field in the areas of scheduling and operating system kernels. Given the vast amount of work that has been done by both the operations research and computer science communities in the scheduling area, we discuss four paradigms underlying the scheduling approaches and present several exemplars of each. The four paradigms are: static tabledriven scheduling, static priority preemptive scheduling, dynamic planningbased scheduling, and dynamic best efSort scheduling. In the operating system context, we argue that most of the proprietary commercial kernels as well as realtime extensions to timesharing operating system kernels do not fit the needs of predictable realtime systems. We discuss several research kernels that are currently being built to explicitly meet the needs of realtime applications.
Synthesis Techniques for LowPower Hard RealTime Systems on Variable Voltage Processors
, 1998
"... The energy efficiency of systemsonachip can be much improved if one were to vary the supply voltage dynamically at run time. In this paper we describe the synthesis of systemsonachip based on core processors, while treating voltage (and correspondingly, the clock frequency) as a variable to be ..."
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Cited by 109 (5 self)
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The energy efficiency of systemsonachip can be much improved if one were to vary the supply voltage dynamically at run time. In this paper we describe the synthesis of systemsonachip based on core processors, while treating voltage (and correspondingly, the clock frequency) as a variable to be scheduled along with the computation tasks during the static scheduling step. In addition to describing the complete synthesis design flow for these variable voltage systems, we focus on the problem of doing the voltage scheduling while taking into account the inherent limitation on the rates at which the voltage and clock frequency can be changed by the power supply controllers and clock generators. Taking these limits on rate of change into account is crucial since changing the voltage by even a volt may take time equivalent to 100s to 10,000s of instructions on modern processors. We present both an exact but impractical formulation of this scheduling problem as a set of nonlinear equations, as well as a heuristic approach based on reduction to an optimally solvable restricted ordered scheduling problem. Using various task mixes drawn from a set of nine reallife applications, our results show that we are able to reduce power consumption to within 7% of the lower bound obtained by imposing no limit at the rate of change of voltage and clock frequencies.
MOGAC: A Multiobjective Genetic Algorithm for HardwareSoftware CoSynthesis of Distributed Embedded Systems
, 1998
"... In this paper, we present a hardwaresoftware cosynthesis system, called MOGAC, that partitions and schedules embedded system specifications consisting of multiple periodic task graphs. MOGAC synthesizes realtime heterogeneous distributed architectures using an adaptive multiobjective genetic algor ..."
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Cited by 94 (6 self)
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In this paper, we present a hardwaresoftware cosynthesis system, called MOGAC, that partitions and schedules embedded system specifications consisting of multiple periodic task graphs. MOGAC synthesizes realtime heterogeneous distributed architectures using an adaptive multiobjective genetic algorithm that can escape local minima. Price and power consumption are optimized while hard realtime constraints are met. MOGAC places no limit on the number of hardware or software processing elements in the architectures it synthesizes. Our general model for bus and pointtopoint communication links allows a number of link types to be used in an architecture. Applicationspecific integrated circuits consisting of multiple processing elements are modeled. Heuristics are used to tackle multirate systems, as well as systems containing task graphs whose hyperperiods are large relative to their periods. The application of a multiobjective optimization strategy allows a single cosynthesis run to ...
COSYN: HardwareSoftware Cosynthesis of Embedded Systems
, 1997
"... Hardwaresoftware cosynthesis is the process of partitioning an embedded system specification into hardware and software modules to meet performance, power, cost, and reliability goals. In this paper, we present a hardwaresoftware cosynthesis technique for realtime distributed embedded systems. ..."
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Cited by 93 (9 self)
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Hardwaresoftware cosynthesis is the process of partitioning an embedded system specification into hardware and software modules to meet performance, power, cost, and reliability goals. In this paper, we present a hardwaresoftware cosynthesis technique for realtime distributed embedded systems. Our cosynthesis algorithm has the following features: 1) it allows the use of multiple types of processing elements (PEs) and interPE communication links, where the links can take various forms (pointtopoint, bus, local area network, etc.), 2) it supports both concurrent and sequential modes of communication and computation, 3) it allows both preemptive and nonpreemptive scheduling, 4) it employs the concept of an association array to tackle the problem of multirate systems (which are commonly found in multimedia applications), 5) it uses a scheduler based on dynamic deadlinebased priority levels for an accurate performance estimation of a cosynthesis solution, 6) it uses a new dynamic...
Powerconscious Joint Scheduling of Periodic Task Graphs and Aperiodic Tasks in Distributed Realtime Embedded Systems
, 2000
"... In this paper , we present a powerconscious algorithm for jointly scheduling multirate periodic task graphs and aperiodic tasks in distributed realtime embedded systems. While the periodic task graphs have hard deadlines, the aperiodic tasks can have either hard or soft deadlines. Periodic task g ..."
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Cited by 72 (2 self)
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In this paper , we present a powerconscious algorithm for jointly scheduling multirate periodic task graphs and aperiodic tasks in distributed realtime embedded systems. While the periodic task graphs have hard deadlines, the aperiodic tasks can have either hard or soft deadlines. Periodic task graphs are first scheduled statically. Slots are created in this static schedule to accommodate hard aperiodic tasks. Soft aperiodic tasks are scheduled dynamically with an online scheduler. Flexibility is introduced into the static schedule and optimized to allow the online scheduler to make dynamic modifications to the static schedule. This helps minimize the response times of soft aperiodic tasks through both resource reclaiming and slack stealing. Of course, the validity of the static schedule is maintained. The online scheduler also employs dynamic voltage scaling and power management to obtain a powerefficient schedule. Experimental results show that the flexibility introduced into the static schedule helps improve the response times of soft aperiodic tasks by up to 43%. Dynamic voltage scaling and power management reduce power by up to 68%. The scheme in which the static schedule is allowed to be flexible achieves up to 32% more power saving compared to the scheme in which no flexibility is allowed, when both schemes are powerconscious. Our work gives an average architecture price saving of 30% over a previous approach for embedded system architectures synthesized with execution slots for hard aperiodic tasks present. 1.
Batteryaware Static Scheduling for Distributed Realtime Embedded Systems
, 2001
"... This paper addresses batteryaware static scheduling in batterypowered distributed realtime embedded systems. As suggested by previous work, reducing the discharge current level and shaping its distribution are essential for extending the battery lifespan. We propose two batteryaware static sc ..."
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Cited by 69 (0 self)
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This paper addresses batteryaware static scheduling in batterypowered distributed realtime embedded systems. As suggested by previous work, reducing the discharge current level and shaping its distribution are essential for extending the battery lifespan. We propose two batteryaware static scheduling schemes. The first one optimizes the discharge power profile in order to maximize the utilization of the battery capacity. The second one targets distributed systems composed of voltagescalable processing elements (PEs). It performs variablevoltage scheduling via efficient slack time reallocation, which helps reduce the average discharge power consumption as well as flatten the discharge power profile. Both schemes guarantee the hard realtime constraints and precedence relationships in the realtime distributed embedded system specification. Based on previous work, we develop a battery lifespan evaluation metric which is aware of the shape of the discharge power profile. Our experimental results show that the battery lifespan can be increased by up to 29% by optimizing the discharge power file alone. Our variablevoltage scheme increases the battery lifespan by up to 76% over the nonvoltagescalable scheme and by up to 56% over the variablevoltage scheme without slacktime reallocation. 1.