This paper introduces the architecture and initial algorithms for Pixel-planes 5, a heterogeneous multi-computer designed both for high-speed polygon and sphere rendering (1M Phong-shaded triangles/second) and for supporting algorithm and application research in interactive 3D graphics. Techniques are described for volume rendering at multiple frames per second, font generation directly from conic spline descriptions, and rapid calculation of radiosity form factors. The hardware consists of up to 32 math-oriented processors, up to 16 rendering units, and a conventional 1280x1024-pixel frame buffer, interconnected by a 5 gigabit ring network. Each rendering unit consists of a 128x128-pixel array of processors-with-memory with parallel quadratic expression evaluation. Implemented on fast custom CMOS chips, this array has 208 bits/pixel on-chip and is connected to a video RAM memory system that provides 4,096 bits of off-chip memory. Rendering units can be independently reassigned to any ...

In a recent alternative research path for interactive 3D graphics the scene to be rendered is described with images. Image-based rendering (IBR) is appealing since natural scenes, which are very difficult to model conventionally, can be acquired semi-automatically using cameras and other devices. Also IBR has the potential to create high-quality output images if the rendering stage can preserve the quality of the reference images (photographs). One promising IBR approach enhances the images with perpixel depth. This allows reprojecting or warping the color-and-depth samples from the reference image to the desired image. Image-based rendering by warping (IBRW) is the focus of this dissertation. In IBRW, simply warping the samples does not suffice for high-quality results because one must reconstruct the final image from the warped samp...

this memory. However, for our hardware multiplier, we might be able to connect one input to one memory, the second input to second memory, and the output to yet another memory. This might be done with very little external circuitry, providing that the algorithm chosen allows for simple address generation schemes. This means that we have achieved very high memory bandwidths at very low cost. The two main drawbacks of specialised hardware are its inflexibility, and the large design effort required. However, until conventional desktop computers become available with a performance several orders of magnitude greater than that which currently exists, this may be the only viable option.