In high-end microprocessors, control-logic timing can gate the cycle time, but control logic is specified late and changes often. Custom design is too time consuming for control implementation, and application specific integrated circuit (ASIC)-like methods have difficulty achieving the required performance /area targets. In this paper, we describe C5M, a new layout system for high-performance control logic which has been successfully used in the design of a recent 400 MHz IBM processor. Results from this design are used to show that C5M achieves near custom quality with high productivity and predictability.

This paper describes a fully automatic standard-cell layout synthesis system, CELLERITY. The system is flexible in supporting a wide variety of process technologies and a range of library template styles. The tool is fully automatic and provides several options to the user to customize the layout template. The tool considers performance and yield and generates dense, design-rule correct layouts. Experimental results indicate that the area of CELLERITY-generated standard cells is competitive with manually designed cells in a majority of circuits. In block-level tests of industrial circuits, standard-cell blocks generated using CELLERITY cells are about equal to the block area produced by using a manually-designed library. Recently, an embedded microcontroller in a state-of-the-art sub-micron process technology was fabricated using CELLERITY-generated standard cells. 1 INTRODUCTION Standard-cell methodology is widely used in IC design. Automation of standard-cell mask layout generation...

We present a novel technique CLIP for optimizing both the height and width of CMOS cell layouts in the two-dimensional (2D) style. CLIP is based on integer-linear programming (ILP) and proceeds in two stages: First, an ILP model is used to determine a 2-D layout of minimum width W cell . Then, another model generates a 2-D layout that has width W cell and requires a minimum number of routing tracks. Run times are in seconds for circuits with up to 16 transistors. For larger circuits, we extend CLIP to a hierarchical method HCLIP that places series-connected transistors contiguously. This reduces run times by up to three orders of magnitude, and still yields optimal results in over 80% of cases. 1 Introduction The objective of cell layout synthesis is to minimize the cell area subject to constraints. For one-dimensional (1-D) layouts, which use a single pair of parallel P and N diffusion rows, minimizing both cell width and height can yield up to 80% savings in area over width minimiz...

We address the problem of CMOS cell width minimization in the general two-dimensional (2-D) layout style and propose a novel technique based on integer linear programming (ILP) to solve it exactly. We formulate a 0-1 ILP model whose solution minimizes cell width along with the routing complexity across the diffusion rows. We present experimental results that evaluate the performance of two ILP solvers that have very different solution methods, and assess the effect of the number of rows on cell width. Runtimes for optimal layouts are in seconds for cells with up to 20 transistors. For larger cells, we propose a practical circuit pre-processing scheme that dramatically reduces the run time with little or no loss in optimality. 1 Introduction Cell synthesis automates cell layout generation, thereby making layout design faster, correct-by-construction, and flexible. While automation can increase productivity, optimal algorithms have generally been avoided in favor of faster but less exac...

A rigorous and efficient technique is presented for module generation in a maximally stacked layout paradigm for CMOS analog integrated circuits. Analog constraints on symmetry and matching provide a key for heuristics substantially reducing the computational complexity of robust graph algorithms. The solution found minimizes a cost function accounting for parasitic control and routability considerations. Combined with sensitivity analysis and automatic constraint generation, this algorithm provides a suitable performance-driven approach to analog layout module generation. Examples are reported showing the effectiveness of our approach. 1. INTRODUCTION In recent years, several approaches to the automatic synthesis of analog integrated circuits have been proposed [1, 2, 3]. Significant efforts have been made toward a consistent performance-driven methodology [4], such that the respect of high-level specifications is guaranteed in all design stages. However, a severe discontinuity is pr...

This paper describes algorithms for automatic layout synthesis of leaf cells in 1--d and in anew 1--1/2--d layout style, useful for non--dual circuit styles. Thegraph theory based algorithms use concepts set forth by Euler and Hamilton to achieve two tasks. The transistor placementalgorithmusestheEuler'stheorem,whilethe placement of the groups of the transistors is achieved by using Hamiltonian graphs. Results show that the algorithms produce extremely competent layouts when compared to other algorithms in the literature and manual layouts.

We present a hierarchical technique, based on integer linear programming (ILP), to generate area-efficient layouts of relatively large complex CMOS cells in the twodimensional (2-D or multi-row) style. First, the CMOS circuit is partitioned into subcircuits called clusters. Next, the set of all minimum-width 1-D placements (chain covers) are generated for each cluster, and form the input to the ILP model. The model aims at selecting exactly one cover for each cluster such that the overall 2-D cell width is minimized. In the process, all possible diffusion sharing between transistor chains belonging to clusters are considered; the inter-row connections that contribute to the overall cell width are also reduced. Experimental results demonstrate that the technique reduces run times by several orders of magnitude over non-hierarchical methods, and yields optimal or near-optimal layouts in most cases. 1 Introduction Cell synthesis techniques can increase design productivity by automating t...

We present a subjective review of custom cell generation methods in the context of future advances in state-of-the-art digital circuit synthesis. In particular, we describe three opportunities for coupling circuit optimization operations with the library development process. These operations include electrical optimization, technology mapping, and cell level place and route. 1.# Introduction Several methods have been developed in recent years for the automatic generation of cell libraries. This effort has been largely motivated by a need for alternatives to manual layout thereby reducing library development costs and time to market. The most common approaches are layout generators, re-compaction of existing libraries, and automatic cell synthesis. Procedural layout generators, which are either languagebased or interfaced with a symbolic layout system, are a means of capturing the layout design in a somewhat designrule independent fashion. This is useful in reducing the layout creati...

A dual-eulerian graph is a plane graph which has an ordering defined on its edge set which forms simultaneously an Euler circuit in the graph and an euler circuit in the dual graph. Dual-eulerian graphs were defined and studied in the context of silicon optimization of cmos layouts. In this paper we examine the connections between the dual eulerian property, Petrie walks, and the connectivity of the graph. We will also consider the dual-eulerian property for graphs embedding in surfaces of higher genus. 1