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35
RAPPID: An Asynchronous Instruction Length Decoder
, 1999
"... This paper describes an investigation of potential advantages and risks of applying an aggressive asynchronous design methodology to Intel Architecture. RAPPID ("Revolving Asynchronous Pentium Processor Instruction Decoder"), a prototype IA32 instruction length decoding and steering unit, ..."
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Cited by 61 (38 self)
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This paper describes an investigation of potential advantages and risks of applying an aggressive asynchronous design methodology to Intel Architecture. RAPPID ("Revolving Asynchronous Pentium Processor Instruction Decoder"), a prototype IA32 instruction length decoding and steering unit, was implemented using selftimed techniques. RAPPID chip was fabricated on a 0.25µ CMOS process and tested successfully. Results show significant advantagesin particular, performance of 2.54.5 instructions/nSwith manageable risks using this design technology. RAPPID achieves three times the throughput and half the latency, dissipating only half the power and requiring about the same area as an existing 400MHz clocked circuit.
Difference decision diagrams
 University of Copenhagen
, 1999
"... This paper describes a new data structure, difference decision diagrams (DDDs), for representing a Boolean logic over inequalities of the form ¡£¢¥¤§¦© ¨ and ¡�¢¥¤���¨ where the variables are integer or realvalued. We give algorithms for manipulating DDDs and for determining functional properties ( ..."
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Cited by 43 (2 self)
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This paper describes a new data structure, difference decision diagrams (DDDs), for representing a Boolean logic over inequalities of the form ¡£¢¥¤§¦© ¨ and ¡�¢¥¤���¨ where the variables are integer or realvalued. We give algorithms for manipulating DDDs and for determining functional properties (tautology, satisfiability, and equivalence). DDDs enable an efficient verification of timed systems modeled as, for example, timed automata or timed Petri nets, since both the states and their associated timing information can be represented symbolically, similar to how ROBDDs represent Boolean predicates.
Efficient Verification of Timed Automata using Dense and Discrete Time Semantics
"... In this paper we argue that the semantic issues of discrete vs. dense time should be separated as much as possible from the pragmatics of statespace representation. Contrary to some misconceptions, the discrete semantics is not inherently bound to use stateexplosive techniques any more than the de ..."
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Cited by 23 (5 self)
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In this paper we argue that the semantic issues of discrete vs. dense time should be separated as much as possible from the pragmatics of statespace representation. Contrary to some misconceptions, the discrete semantics is not inherently bound to use stateexplosive techniques any more than the dense one. In fact, discrete timed automata can be analyzed using any representation scheme (such as DBM) used for dense time, and in addition can bene t from enumerative andsymbolic techniques (such as BDDs) which are not naturally applicable to dense time. DBMs, on the other hand, can still be used more e ciently by taking into account theactivity of clocks, to eliminate redundancy. To support these claims we report experimental results obtained using an extension of Kronos with BDDs and variabledimension DBMs where we veri ed the asynchronous chip STARI, a FIFO bu er which provides for skewtolerant communication between two synchronous systems. Using discrete time and BDDs we were able to prove correctness of a STARI implementation with 18 stages (55 clocks), better than what has been achieved using other techniques. The veri cation results carry over to the dense semantics. Using variabledimension DBMs we havemanaged to verify STARI for up to 8 stages (27 clocks). In fact, our analysis shows that at most one third of the clocks are active atanyreachable state, and about one fourth of the clocks are active in 90 % of the reachable states.
Timed trace theoretic verification using partial order reduction
 Proc. of Fifth International Symposium on Advanced Research in Asynchronous Circuits and Systems
, 1999
"... In this paper, we have extended the trace theoretic verification method with partial order reduction so that it can properly handle timed circuits and timed specification. The partial order reduction algorithm is obtained from the timed version of the Stubborn set method. The experimental results wi ..."
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Cited by 20 (10 self)
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In this paper, we have extended the trace theoretic verification method with partial order reduction so that it can properly handle timed circuits and timed specification. The partial order reduction algorithm is obtained from the timed version of the Stubborn set method. The experimental results with the STARI circuits show that the proposed method works very efficiently. 1
Formal Verification of Safety Properties in Timed Circuits
, 2000
"... The incorporation of timing makes circuit verification computationally expensive. This paper proposes a new approach for the verification of timed circuits. Rather than calculating the exact timed state space, a conservative overestimation that fulfills the property under verification is derived. Ti ..."
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Cited by 17 (6 self)
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The incorporation of timing makes circuit verification computationally expensive. This paper proposes a new approach for the verification of timed circuits. Rather than calculating the exact timed state space, a conservative overestimation that fulfills the property under verification is derived. Timing analysis with absolute delays is efficiently performed at the level of event structures and transformed into a set of relative timing constraints. With this approach, conventional symbolic techniques for reachability analysis can be efficiently combined with timing analysis. Moreover, the set of timing constraints used to prove the correctness of the circuit can also be reported for backannotation purposes. Some preliminary results obtained by a naive implementation of the approach show that systems with more than 10^6 untimed states can be verified.
Timed circuits: A new paradigm for highspeed design
 in Proc. of Asia and South Pacific Design Automation Conference
, 2001
"... Abstract — In order to continue to produce circuits of increasing speeds, designers must consider aggressive circuit design styles such as selfresetting or delayedreset domino circuits used in IBM’s gigahertz processor (GUTS) and asynchronous circuits used in Intel’s RAPPID instruction length deco ..."
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Cited by 16 (11 self)
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Abstract — In order to continue to produce circuits of increasing speeds, designers must consider aggressive circuit design styles such as selfresetting or delayedreset domino circuits used in IBM’s gigahertz processor (GUTS) and asynchronous circuits used in Intel’s RAPPID instruction length decoder. These new timed circuit styles, however, cannot be efficiently and accurately analyzed using traditional static timing analysis methods. This lack of efficient analysis tools is one of the reasons for the lack of mainstream acceptance of these design styles. This paper discusses several industrial timed circuits and gives an overview of our timed circuit design methodology. I.
Timed Circuit Verification Using TEL Structures
 IEEE Transactions on ComputerAided Design of Integrated Circuits
, 2001
"... Abstract—Recent design examples have shown that significant performance gains are realized when circuit designers are allowed to make aggressive timing assumptions. Circuit correctness in these aggressive styles is highly timing dependent and, in industry, they are typically designed by hand. In ord ..."
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Cited by 16 (6 self)
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Abstract—Recent design examples have shown that significant performance gains are realized when circuit designers are allowed to make aggressive timing assumptions. Circuit correctness in these aggressive styles is highly timing dependent and, in industry, they are typically designed by hand. In order to automate the process of designing and verifying timed circuits, algorithms for their synthesis and verification are necessary. This paper presents timed event/level (TEL) structures, a specification formalism for timed circuits that corresponds directly to gatelevel circuits. It also presents an algorithm based on partially ordered sets to make the statespace exploration of TEL structures more tractable. The combination of the new specification method and algorithm significantly improves efficiency for gatelevel timing verification. Results on a number of circuits, including many from the recently published gigahertz unit Test Site (guTS) processor from IBM indicate that modules of significant size can be verified using a level of abstraction that preserves the interesting timing properties of the circuit. Accurate circuit level verification allows the designer to include less margin in the design, which can lead to increased performance. I.
Partial Order reduction for Model Checking of Timed Automata
, 1999
"... Abstract. The paper presents a partial order reduction method applicable to networks of timed automata. The advantage of the method is that it reduces both the number of explored control states and the number of generated time zones. The approach is based on a localtime semantics for networks of ti ..."
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Cited by 16 (0 self)
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Abstract. The paper presents a partial order reduction method applicable to networks of timed automata. The advantage of the method is that it reduces both the number of explored control states and the number of generated time zones. The approach is based on a localtime semantics for networks of timed automata defined by Bengtsson et al. [1998], and used originally for local reachability analysis. In this semantics, each component automaton executes asynchronously, in its own local time scale, which is tracked by an auxiliary reference clock. On communication transitions, the automata synchronize their time scales. We show how this model can be used to perform model checking for an extension of linear temporal logic, which can express timing relations between events. We also show how for a class of timed automata, the localtime model can be implemented using difference bound matrices without any space penalty, despite the need to represent local time. Furthermore, we analyze the dependence relation between transitions in the new model and give practical conditions for selecting a reduced set of transitions. 1
Hofstee. Verification of DelayedReset Domino Circuits using ATACS
 In 1999 International Workshop on Timing Issues in the Specification and Synthesis of Digital Systems (TAU99
, 1999
"... This paper discusses the application of the timing analysis tool ATACS to the high performance, selfresetting and delayedreset domino circuits being designed at IBM’s Austin Research Laboratory. The tool, which was originally developed to deal with asynchronous circuits, is well suited to the self ..."
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Cited by 11 (2 self)
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This paper discusses the application of the timing analysis tool ATACS to the high performance, selfresetting and delayedreset domino circuits being designed at IBM’s Austin Research Laboratory. The tool, which was originally developed to deal with asynchronous circuits, is well suited to the selfresetting style since internally, a block of selfresetting or delayedreset domino logic is asynchronous. The circuits are represented using timed event/level structures. These structures correspond very directly to gate level circuits, making the translation from a transistor schematic to a TEL structure straightforward. The statespace explosion problem is mitigated using an algorithm based on partially ordered sets (POSETs). Results on a number of circuits from the recently published guTS (gigahertz unit Test Site) processor from IBM indicate that modules of significant size can be verified with ATACS using a level of abstraction that preserves the interesting timing properties of the circuit. Accurate circuit level verification allows the designer to include less margin in the design, which can lead to increased performance. 1
Algorithms For Synthesis And Verification Of Timed Circuits And Systems
, 1999
"... In order to increase performance, circuit designers are beginning to move away from traditional, synchronous designs based on static logic. Recent design examples have shown that significant performance gains are realized when aggressive circuit styles are used. Circuit correctness in these aggressi ..."
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Cited by 11 (2 self)
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In order to increase performance, circuit designers are beginning to move away from traditional, synchronous designs based on static logic. Recent design examples have shown that significant performance gains are realized when aggressive circuit styles are used. Circuit correctness in these aggressive circuit styles is highly timing dependent, and in industry they are typically designed by hand. In order to automate the process of designing and verifying timed circuits, algorithms to explore the reachable state space of the circuit under the timing constraints are necessary. This thesis presents a new specification method for timed circuits, timed event/level (TEL) structures, and new algorithms for exploring a timed state space. The TEL structure specification allows the designer to specify behavior controlled by signal transitions, which is best for representing sequencing, and behavior controlled by signal levels, which is best for representing gate level circuits. This thesis also...