This paper introduces the Field-Programmable Learning Array, a new paradigm for rapid prototyping of learning primitives and machinelearning algorithms in silicon. The FPLA is a mixed-signal counterpart to the all-digital Field-Programmable Gate Array in that it enables rapid prototyping of algorithms in hardware. Unlike the FPGA, the FPLA is targeted directly for machine learning by providing local, parallel, online analog learning using floating-gate MOS synapse transistors. We present a prototype FPLA chip comprising an array of reconfigurable computational blocks and local interconnect. We demonstrate the viability of this architecture by mapping several learning circuits onto the prototype chip. 1

This paper is a tutorial introduction to field-programmable analog arrays, as well as a review of existing field-programmable analog array architectures, of both educational and industrial origin. Circuit issues relevant to the development of high-bandwidth FPAAs are presented. A current conveyor-based architecture, which promises to achieve video bandwidths, is described. Test results are presented for the CMOS current conveyor-based FPAA building block, with programmable transconductors and capacitors. Measurements indicate bandwidths in excess of 10MHz, and functionality of amplifiers, integrators, differentiators, and adders. The die area is 1.5mm x 3.5mm in a 0.8μm CMOS technology. 1.

In this paper, we present a rapid prototyping environment for mixed signal systems. The environment consists of programmable mixed signal hardware together with a set of integrated CAD tools to enable fast prototyping of mixed signal designs from high-level specifications. The prototyping hardware comprises of field-programmable analog arrays and field-programmable gate arrays on which the analog and digital sections of the design are respectively implemented. Field-programmable interconnect routes signals between multiple devices. A bank of data converters constitutes the interface between the analog and digital parts. Design tools are required to map the given design onto the prototyping hardware. The high-level design specification is first compiled into an intermediate format suitable for synthesis. Following this, the design is partitioned into analog and digital sections. The analog and digital subsystems are synthesized for the target FPAA and FPGA devices respectively. Configur...

The purpose of this project is to overcome the limitations of current neural network chips which generally have poor reconfigurability, and lack parameters for efficient learning. A new general-purpose analog neural network design is made for the TSMC 0.35um CMOS process. Parallel processing is possible with a massive array of independent cells, concurrently processing data. This allows the network to quickly recognize information in various applications. With support for multiple learning algorithms, arbitrary routing, high density, and storage of many parameters using improved high-resolution analog multi-valued memory, this network is suitable for vast improvements to the learning algorithms. Such improvements allow learning to interact with routing for a network which is not bound to a fixed layout. Other improvements include the interaction of multiple learning algorithms to learn partially by pattern, and partially by feedback. Modified Backpropagation learning used with the learning rate parameters allows important data to be reinforced and retained, and insignificant data to be labile, providing improved learning speed. In addition to introducing the planned design for chip implementation, an op-amp prototype is created on a PC board. This prototype allows further development at cell-level, as well as a demonstration of the operation of the CMOS chip. SPICE is used for simulations of the CMOS circuit cells to determine accuracy and input/output range. Neuron circuits were found to be accurate, as was the Gilbert multiplier when input range was restricted. Neuron and synapse circuit design is complete, now in the simulation and layout phase.

ACKNOWLEDGMENTS I would like to thank everyone who helped me along the way from my advisor, Paul Hasler, to my colleagues within the CADSP research group. I would also like to thank my friends and family who encouraged me throughout the process. However, my greatest thanks goes to my ever loving wife, Shannon, who has endured many things throughout my graduate life that I have no doubt caused. I could never have managed through these last few years without her love, support, and most of all, patience.

Systems on chip, by definition, unite a number of functions and occasionally, sensors or actuators, into a unified, compact, lower-power solution to a signal processing problem. Recent efforts have seen the research, development, and commercialization of systems on chip that are sufficiently programmable and flexible to address a wider variety of applications and signal processing problems than their fixed configuration counterparts. In this paper, we present the application of a recently commercialized SoC effort to the problem of interrogating a low frequency radio frequency transponder, using an amplitude shift keyed encoding scheme. Within this representative application, the following reductions are realized compared to a discrete implementation: power 64%, cost 71%, component count 96%, and size 95%. In addition, the better matched components in the SoC provide a 25 % improvement in read range over the discrete implementation of the radio frequency identification interrogator.

An overview of a simulation strategy for the verification of one of the first mixed-signal field-programmable system on a chip (FPSOC) is presented. The FPSOC integrates a microcontroller, FLASH memory, programmable digital blocks, and programmable analog blocks. A proprietary digital Verilog with analog extensions was used to verify system interactions between the analog and digital blocks. First-pass functional silicon was obtained because of the simulation methodology.

In this thesis a new signal processing technique is presented. This technique exploits the use of pulses as the signalling mechanism. This Palmo 1 signalling method applied to signal processing is novel, combining the advantages of both digital and analogue techniques. Pulsed signals are robust, inherently low-power, easily regenerated, and easily distributed across and between chips. The Palmo cells used to perform analogue operations on the pulsed signals are compact, fast, simple and programmable.

Abstract—The modulation and demodulation blocks in an orthogonal frequency-division multiplexing (OFDM) system are typically implemented digitally using a fast Fourier transform circuit. We propose an analog implementation of an OFDM demodulator as a means for reducing power consumption. The proposed receiver implements the discrete Fourier transform (DFT) as a vector–matrix multiplier using floating-gate transistors on a field-programmable analog array (FPAA). The DFT coefficients can be tuned to counteract an inherent device mismatch by adjusting the amount of electrical charge stored in the floating-gate transistors. When compared to a digital field-programmable gate array implementation, the analog FPAA implementation of the DFT reduces power consumption at the cost of a slight performance degradation. Considering the errors in the DFT coefficients as intersymbol interference, the performance degradation can be further mitigated by employing a least mean-square or minimum mean-square-error equalizer. Index Terms—Discrete Fourier transform (DFT), fast Fourier transform (FFT), field-programmable analog array (FPAA), floating-gate transistor, intersymbol interference (ISI), least mean square (LMS), minimum mean square error (MMSE), orthogonal frequency-division multiplexing (OFDM), vector–matrix multiplier (VMM). I.

Date Approved: August 23, 2011Any intelligent fool can make things bigger, more complex, and more violent. It takes a touch of genius-- and a lot of courage-- to move in the opposite direction.-- Albert EinsteinTo all my sweet family and my beloved wife with the most gratitude that I feel stuck that I cannot show it enoughACKNOWLEDGEMENTS I would first like to express the most gratitude to my advisor, Prof. John Barry, for his encouragement and support during my time at Georgia Tech. He not only has brightened the way when I was totally lost in finding a lighthouse for my research, but also has continuously inspired me with the guidance for my life. I deeply appreciate every opportunity I had to speak with him and learn from him in person. I learned a lot from his rigorous thought process in defining problems, modeling systems, and solving the problems, which will affect me in one way or another throughout the rest of my research activities. I am also indebted to my co-advisor, Prof. Paul Hasler, who has guided me with his invaluable insights on circuit implementation aspects. Being able to be involved in actual circuit implementation was a great advantage for me to maintain a close distance from practical issues. His advice and directions meant a lot to me whenever I was struggling with