Citation Context

...tes ∼30% frequency tuning range for a latch-based FPU, in 130nm CMOS, to combat process variation effects. Subsequently, we explored the potential benefits of VI using a standard VLSI-CAD design flow =-=[6]-=-, by leveraging Synopsys Design Compiler [7] to cut blocks of combinational logic into substages for flip-flop based designs. We show that VI can achieve a nominal frequency target after process varia...

Citation Context

...core CMP machine [29, 30]. Our recent efforts explore the optimal selection of voltage cut-points for the interpolation technique when considering tradeoffs in terms of power overheads and tunability =-=[31]-=-. Process variations are especially problematic for memory designs, which rely on the smallest featuresize transistors. Recent results from Intel show that traditional 6T memory cells are not scaling ...

Citation Context

...ted as one of the “Top Picks in Computer Architecture in 2008” for IEEE Micro magazine [34]. We have also explored power-saving techniques for deeply pipelined architectures using this prototype chip =-=[35]-=- While our chip implementation successfully demonstrated the concept of variable latency and voltage interpolation, there are many questions related to the design of systems that utilize voltage inter...