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32
Performance Analysis of Carbon Nanotube Interconnects for VLSI Applications
, 2005
"... The work in this paper analyses the applicability of carbon nanotube (CNT) bundles as interconnects for VLSI circuits, while taking into account the practical limitations in this technology. A model is developed to calculate equivalent circuit parameters for a CNTbundle interconnect based on interc ..."
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Cited by 32 (6 self)
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The work in this paper analyses the applicability of carbon nanotube (CNT) bundles as interconnects for VLSI circuits, while taking into account the practical limitations in this technology. A model is developed to calculate equivalent circuit parameters for a CNTbundle interconnect based on interconnect geometry. Using this model, the performance of CNTbundle interconnects (at local, intermediate and global levels) is compared to copper wires of the future. It is shown that CNT bundles can outperform copper for long intermediate and global interconnects, and can be engineered to compete with copper for local level interconnects. The technological requirements necessary to make CNT bundles viable as future interconnects are also laid out.
A global interconnect optimization scheme for nanometer scale vlsi with implications for latency, bandwidth, and power dissipation
 IEEE Trans. of Electron Devices
, 2004
"... Abstract—This paper addresses the critical problem of global wire optimization for nanometer scale very large scale integration technologies, and elucidates the impact of such optimization on power dissipation, bandwidth, and performance. Specifically, this paper introduces a novel methodology for o ..."
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Cited by 27 (1 self)
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Abstract—This paper addresses the critical problem of global wire optimization for nanometer scale very large scale integration technologies, and elucidates the impact of such optimization on power dissipation, bandwidth, and performance. Specifically, this paper introduces a novel methodology for optimizing global interconnect width, which maximizes a novel figure of merit (FOM) that is a userdefined function of bandwidth per unit width of chip edge and latency. This methodology is used to develop analytical expressions for optimum interconnect widths for typical FOMs for two extreme scenarios regarding line spacing: 1) spacing kept constant at its minimum value and 2) spacing kept the same as line width. These expressions have been used to compute the optimal global interconnect width and quantify the effect of increasing the line width on various performance metrics such as delay per unit length, total repeater area and power dissipation, and bandwidth for various International Technology Roadmap for Semiconductors technology nodes. Index Terms—Bandwidth, critical inductance, delay per unit
Power supply optimization in sub130nm leakage dominant technologies
 Proc. Int’l Symp. Quality Electronic Design
, 2004
"... In this paper we present a methodology for systematically optimizing the power supply voltage for maximizing the performance of VLSI circuits in technologies where leakage power is not an insignificant fraction of the total power dissipation. For this purpose, we develop simplified empirical equatio ..."
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Cited by 6 (0 self)
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In this paper we present a methodology for systematically optimizing the power supply voltage for maximizing the performance of VLSI circuits in technologies where leakage power is not an insignificant fraction of the total power dissipation. For this purpose, we develop simplified empirical equations which describe the transistor behaviour as a function of power supply and temperature. We use these models to calculate the fullchip power dissipation as a function of power supply and temperature. We then solve the power and chip thermal equations simultaneously to calculate the chip temperature and power dissipation at a given power supply. By varying the power supply voltage we determine the optimum VDD value which minimized delay per unit length in global interconnects and therefore maximizes performance. We show that for 90 nm and 65 nm technologies where leakage power represents a significant fraction of the total power dissipation, optimum VDD is lower than the ITRS specified supply voltage. This is due to the fact that reducing VDD results in a large reduction in total power dissipation and therefore the chip temperature which improves performance. This improvement in performance is greater than the performance penalty incurred due to reduction in VDD. 1
Estimation of signal integrity loss through reduced order interconnect model
 in 7th Workshop on Signal Propagation on Interconnects, IEEE
, 2003
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Modeling and analysis of crosstalk coupling effect on the victim interconnect using the ABCD network model.
 In Proceedings of the 19th IEEE International Symposium on Defect and Fault Tolerance in VLSI Systems (DFT’04),
, 2004
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Analysis of Crosstalk Coupling Effects between Agressor and Victim Interconnect using Twoport Network Model
 in 8th IEEE Workshop on Signal Propagation on Interconnects, May 9th12th 2004
"... Signal Integrity (SI) losses in the interconnects are the disturbances coming out of their distributed nature of parasitic capacitances, resistances, and inductances at high frequency operation [1]. SI losses are further aggravated if multiple interconnect lines couple energy from, or to each other. ..."
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Cited by 2 (1 self)
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Signal Integrity (SI) losses in the interconnects are the disturbances coming out of their distributed nature of parasitic capacitances, resistances, and inductances at high frequency operation [1]. SI losses are further aggravated if multiple interconnect lines couple energy from, or to each other. Therefore, this paper aims to analyze the crosstalk coupling effects between the two interconnects, namely the aggressor and victim lines, using the ABCD twoport network model. In order to reduce the simulation time a reduced order modeling of the interconnect line is considered. Furthermore, as stated in various literatures [7] the rising (or falling) input signal represented by a simple step function is not accurate enough, therefore in this paper the rising transitions and the falling transitions are represented more accurately using the exponential terms, and based on such input representation the time domain output signal voltage in presence of crosstalk noise, at the far end side of both aggressor line and victim line, is determined. Such output voltage representation is very helpful in estimating the delay, overshoot or undershoot etc., which are believed to cause SI losses in the SoC. 1.
Modeling of the performance of carbon nanotube bundle, cu/lowk and optical onchip global interconnects
 In SLIP ’07: Proceedings of the 2007 international workshop on System level interconnect prediction
, 2007
"... In this work, we have quantified and compared the performance of carbon nanotube (CNT) and optical interconnects with the existing technology of Cu/lowK interconnects for future highperformance ICs. We present these comparisons not only in terms of commonly used metrics such as latency and power d ..."
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In this work, we have quantified and compared the performance of carbon nanotube (CNT) and optical interconnects with the existing technology of Cu/lowK interconnects for future highperformance ICs. We present these comparisons not only in terms of commonly used metrics such as latency and power dissipation, but also compare them using important compound performance metrics, such as, bandwidth density per latency per power. We find that the optical interconnect has the lowest latency for global interconnects and the highest achievable bandwidth density using wavelength division multiplexing. However, the value of the compound metric is the highest for either CNTs or optical technology depending on the required bandwidth density. Both these technologies significantly outperform the existing Cu/lowK interconnect technology. We have also extensively examined the impact of device, material, and system parameters of the novel interconnect technologies on the comparisons. We find that using small detector and modulator capacitances optical interconnects (~10fF) yield superior performance compared to CNTs (electron mean free path of 0.9μm) and Cu for switching activities greater than 35 % and 20%, respectively. However, improving mean free path of CNTs to ~2.8μm increases the crossover switching activity to 80%.
Effect of inductance on interconnect propagation delay
 in VLSI circuits,” Proc. of 8th Workshop on SPI, 121–124
, 2004
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Closed form Delay Model for onChip VLSI RLCG Interconnects for Ramp Input for Different Damping Conditions
"... Abstract—Fast delay estimation methods, as opposed to simulation techniques, are needed for incremental performance driven layout synthesis. Onchip inductive effects are becoming predominant in deep submicron interconnects due to increasing clock speed and circuit complexity. Inductance causes nois ..."
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Cited by 1 (1 self)
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Abstract—Fast delay estimation methods, as opposed to simulation techniques, are needed for incremental performance driven layout synthesis. Onchip inductive effects are becoming predominant in deep submicron interconnects due to increasing clock speed and circuit complexity. Inductance causes noise in signal waveforms, which can adversely affect the performance of the circuit and signal integrity. Several approaches have been put forward which consider the inductance for onchip interconnect modelling. But for even much higher frequency, of the order of few GHz, the shunt dielectric lossy component has become comparable to that of other electrical parameters for high speed VLSI design. In order to cope up with this effect, onchip interconnect has to be modelled as distributed RLCG line. Elmore delay based methods, although efficient, cannot accurately estimate the delay for RLCG interconnect line. In this paper, an accurate analytical delay model has been derived, based on first and second moments of RLCG interconnection lines. The proposed model considers both the effect of inductance and conductance matrices. We have performed the simulation in 0.18μm technology node and an error of as low as less as 5 % has been achieved with the proposed model when compared to SPICE. The importance of the conductance matrices in interconnect modelling has also been discussed and it is shown that if G is neglected for interconnect line modelling, then it will result an delay error of as high as 6 % when compared to SPICE.