Results 1 - 10
of
16
3-D ICs: A Novel Chip Design for Improving Deep-Submicrometer Interconnect Performance and Systems-on-Chip Integration
- Proceedings of the IEEE
, 2001
"... This paper analyzes the limitations of the existing interconnect technologies and design methodologies and presents a novel three-dimensional (3-D) chip design strategy that exploits the vertical dimension to alleviate the interconnect related problems and to facilitate heterogeneous integration of ..."
Abstract
-
Cited by 164 (16 self)
- Add to MetaCart
(Show Context)
This paper analyzes the limitations of the existing interconnect technologies and design methodologies and presents a novel three-dimensional (3-D) chip design strategy that exploits the vertical dimension to alleviate the interconnect related problems and to facilitate heterogeneous integration of technologies to realize a system-on-a-chip (SoC) design. A comprehensive analytical treatment of these 3-D ICs has been presented and it has been shown that by simply dividing a planar chip into separate blocks, each occupying a separate physical level interconnected by short and vertical interlayer interconnects (VILICs), significant improvement in performance and reduction in wire-limited chip area can be achieved, without the aid of any other circuit or design innovations. A scheme to optimize the interconnect distribution among different interconnect tiers is presented and the effect of transferring the repeaters to upper Si layers has been quantified in this analysis for a two-layer 3-D
Analysis of substrate thermal gradient effects on optimal buffer insertion
- In ICCAD
, 2001
"... Abstract. This paper studies the effects of the substrate thermal gradients on the buffer insertion techniques. Using a non-uniform temperaturedependent distributed RC interconnect delay model, the buffer insertion problem is analyzed and design guidelines are provided to ensure the nearoptimality o ..."
Abstract
-
Cited by 5 (2 self)
- Add to MetaCart
(Show Context)
Abstract. This paper studies the effects of the substrate thermal gradients on the buffer insertion techniques. Using a non-uniform temperaturedependent distributed RC interconnect delay model, the buffer insertion problem is analyzed and design guidelines are provided to ensure the nearoptimality of the signal performance in the presence of the thermal gradients. In addition, the effect of temperature-dependent driver resistance on the buffer insertion is studied. Experimental results show that neglecting thermal gradients in the substrate and the interconnect lines can result in non-optimal solutions when using standard buffer insertion techniques and that these effects intensify with technology scaling. 1
Inductance aware interconnect scaling
- in Proceedings IEEE International Symposium on Quality Electronic Design
, 2002
"... This paper introduces a new global-tier interconnect scaling scheme which ensures that inductance effects do not start domi-nating the overall interconnect performance. It is shown that for unscaled global lines, inductance effects increase as technology scales while for the scaling scheme proposed ..."
Abstract
-
Cited by 5 (2 self)
- Add to MetaCart
(Show Context)
This paper introduces a new global-tier interconnect scaling scheme which ensures that inductance effects do not start domi-nating the overall interconnect performance. It is shown that for unscaled global lines, inductance effects increase as technology scales while for the scaling scheme proposed by ITRS [1], inter-connects become extremely resistive and, while inductance effects diminish with scaling but the performance, specifically, delay per unit length, degrades with scaling. The effect of the proposed global interconnect scaling scheme on optimized driver size, in-terconnect length, delay per unit length and total buffer area is quantified and compared with the unscaled and the ITRS cases. It is shown that the proposed scaling scheme improves the delay per unit length without degrading inductive effects or increasing buffer area with scaling. 1
Transient Simulation of On-Chip Transmission Lines via Exact Pole Extraction
"... Abstract — An accurate and efficient solution for the transient response at the far end of a transmission line is proposed in this paper. Unlike approximating the poles by truncating the transfer function or matching moments, the exact poles of an interconnect system are analytically extracted. Exce ..."
Abstract
-
Cited by 1 (1 self)
- Add to MetaCart
(Show Context)
Abstract — An accurate and efficient solution for the transient response at the far end of a transmission line is proposed in this paper. Unlike approximating the poles by truncating the transfer function or matching moments, the exact poles of an interconnect system are analytically extracted. Excellent match is observed between the proposed method and Spectre simulations. With two pairs of poles, the average error for the 50 % delay is 1%. Higher accuracy can be obtained with additional pairs of poles. The computational complexity of the model is proportional to the number of pole pairs. I.
An RLC Interconnect Model Based on Fourier Analysis
"... Abstract—Based on a Fourier series analysis, an analytic interconnect model is presented which is suitable for periodic signals, such as a clock signal. In this model, the far-end time-domain waveform is approximated by the summation of several sinusoids. Closed-form solutions of the 50 % delay and ..."
Abstract
- Add to MetaCart
(Show Context)
Abstract—Based on a Fourier series analysis, an analytic interconnect model is presented which is suitable for periodic signals, such as a clock signal. In this model, the far-end time-domain waveform is approximated by the summation of several sinusoids. Closed-form solutions of the 50 % delay and overshoots/undershoots are provided when the fifth and higher order harmonics are ignored. Good accuracy is observed between the model and SPICE simulations. The model is applied to resistance–capacitance–inductance interconnect trees and the computational complexity of the model is linear with the size of the tree and the model order. The tree model is shown to be an effective method to analyze clock distribution networks. The single interconnect model is also extended to coupled multi-interconnect systems to analyze crosstalk noise and a general waveform solution is obtained. It is noted that in addition to the transition time, the period of the aggressor signal also has a significant effect on the crosstalk noise. Index Terms—Clock tree synthesis, Fourier analysis, interconnect, noise analysis, resistance–capacitance–inductance (RLC),
INTEGRATION, the VLSI journal 38 (2004) 205–225 Optimum wire sizing of RLC interconnect with repeaters
"... Repeaters are often used to drive high impedance interconnects. These lines have become highly inductive and can affect signal behavior. The line inductance should therefore be considered in determining the optimum number and size of the repeaters driving a line. The optimum repeater system uses uni ..."
Abstract
- Add to MetaCart
Repeaters are often used to drive high impedance interconnects. These lines have become highly inductive and can affect signal behavior. The line inductance should therefore be considered in determining the optimum number and size of the repeaters driving a line. The optimum repeater system uses uniform repeater insertion in order to achieve the minimum propagation delay. A tradeoff exists, however, between the transient power dissipation and the minimum propagation delay in sizing long interconnects driven by the optimum repeater system. Optimizing the line width to achieve the minimum power delay product, however, can satisfy current high speed, low-power design objectives. A reduction in power of 65 % and delay of 97 % is achieved for an example repeater system. The Power-Delay-Area-Product (PDAP) criterion is introduced as an efficient technique to size the interconnect within a repeater system. A reduction in buffer area of 67 % and interconnect area of 46 % is achieved based on the PDAP. r 2004 Elsevier B.V. All rights reserved.
Published by license under the OCP Science imprint, a member of the Old City Publishing Group Crosstalk Reduction by Voltage Scaling in Global VLSI Interconnects
"... Reprints available directly from the publisher ..."
Analysis of Substrate Thermal Gradient Effects on Optimal Buffer Insertion
- In ICCAD
, 2001
"... This paper studies the effects of the substrate thermal gradients on the buffer insertion techniques. Using a non-uniform temperaturedependent distributed RC interconnect delay model, the buffer insertion problem is analyzed and design guidelines are provided to ensure the nearoptimality of the sign ..."
Abstract
- Add to MetaCart
This paper studies the effects of the substrate thermal gradients on the buffer insertion techniques. Using a non-uniform temperaturedependent distributed RC interconnect delay model, the buffer insertion problem is analyzed and design guidelines are provided to ensure the nearoptimality of the signal performance in the presence of the thermal gradients. In addition, the effect of temperature-dependent driver resistance on the buffer insertion is studied. Experimental results show that neglecting thermal gradients in the substrate and the interconnect lines can result in non-optimal solutions when using standard buffer insertion techniques and that these effects intensify with technology scaling.
