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Receiver-less optical clock injection for clock distribution networks
- IEEE J. Sel. Topics Quantum Electron
, 2003
"... Abstract—We present a new technique of injecting clocks opti-cally onto CMOS chips without the use of a receiver amplifier. We discuss the benefits of such a direct approach and present proof-of-principle experiments of the technique. We analytically compare a receiver-less optical clock distributio ..."
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Cited by 11 (3 self)
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Abstract—We present a new technique of injecting clocks opti-cally onto CMOS chips without the use of a receiver amplifier. We discuss the benefits of such a direct approach and present proof-of-principle experiments of the technique. We analytically compare a receiver-less optical clock distribution and an electrical clock dis-tribution in a fan-out-of-four clock tree to evaluate the timing and power benefits of the optical approach for present microproces-sors. We also compare receiver-less direct injection of optical clocks to trans-impedance receiver based injection within the same distri-bution framework. Index Terms—CMOS integrated circuits, optical clock dis-tribution, receiver-less clock injection, short optical pulses, trans-impedance receivers. I.
Optical Interconnects To Silicon Chips Using Short Pulses
, 2002
"... Processor speeds continue to increase rapidly due to the scaling of CMOS line-widths, but electrical interconnect speeds have not grown at the same rate. The loss mechanisms in electrical interconnects limit their ultimate capacity. Optical interconnects have the potential to alleviate this intercon ..."
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Cited by 2 (0 self)
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Processor speeds continue to increase rapidly due to the scaling of CMOS line-widths, but electrical interconnect speeds have not grown at the same rate. The loss mechanisms in electrical interconnects limit their ultimate capacity. Optical interconnects have the potential to alleviate this interconnect bottleneck. At short scales such as board-to-board, chip-to-chip, and on-chip, the important requirements for these optical interconnects are low latency, high throughput, high density, high bandwidth, and simple integration with mainstream silicon technology. This thesis investigates optical interconnects designed to meet these requirements using short pulses, in conjunction with multiple quantum well (MQW) diodes filp-chip bonded to silicon CMOS chips. The use of short optical pulses (100 fs to a few ps), equivalent to a return-to-zero (RZ) format with very low duty cycle, has many potential advantages. We show that using short pulses in optical links can, a) enhance the sensitivity of the receiver
Empirical Validation of Yield Recovery Using Idle-Cycle Insertion
"... &A TRANSITION FAULT model typically guides test pattern generation to cover defects that cause late signal transitions.1 Such a delay test requires a two-pattern test: The first pattern initializes a node signal value. The second pattern causes this value to switch to the opposite value and sens ..."
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Cited by 1 (0 self)
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&A TRANSITION FAULT model typically guides test pattern generation to cover defects that cause late signal transitions.1 Such a delay test requires a two-pattern test: The first pattern initializes a node signal value. The second pattern causes this value to switch to the opposite value and sensitize the transition to an observable output. These two events should happen on two successive clock pulses at the rated speed of the devices. These two clock pulses are responsible for launching and capturing the transition, respectively. Two scan-based delay test protocols are supported bymost commercial ATPG tools: launch on shift (LOS) and launch on capture (LOC). In LOS test patterns, scan data is loaded through scan chains. Nodes in the logic under test are initialized at the last shift clock (the
Low Power Repeaters Driving RLC Interconnects with Delay and Bandwidth Constraints
"... Abstract — Interconnect plays an increasingly important role in deep submicrometer VLSI technologies. Multiple design criteria are considered in interconnect design, such as delay, power, and bandwidth. In this paper, the effects of inductance on the delay, bandwidth, and power of an RLC interconnec ..."
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Abstract — Interconnect plays an increasingly important role in deep submicrometer VLSI technologies. Multiple design criteria are considered in interconnect design, such as delay, power, and bandwidth. In this paper, the effects of inductance on the delay, bandwidth, and power of an RLC interconnect with repeaters are analyzed. A repeater insertion methodology is presented for achieving the minimum power in an RLC interconnect while satisfying delay and bandwidth constraints. By including inductance, the minimum interconnect power under a delay and/or bandwidth constraint decreases as compared with an RC interconnect. I.
Low Power Repeaters Driving Interconnects with Delay and Bandwidth Constraints
"... Abstract — A repeater insertion methodology is presented for achieving the minimum power in an ¢¤ £ interconnect while satisfying delay and bandwidth constraints. With delay constraints, closed form solutions for the minimum power are developed which are within 10 % of SPICE. With bandwidth constrai ..."
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Abstract — A repeater insertion methodology is presented for achieving the minimum power in an ¢¤ £ interconnect while satisfying delay and bandwidth constraints. With delay constraints, closed form solutions for the minimum power are developed which are within 10 % of SPICE. With bandwidth constraints, the minimum power can be achieved with minimum sized repeaters. I.
Low-Power Repeaters Driving RC and RLC Interconnects With Delay and Bandwidth Constraints
"... Abstract—Interconnect plays an increasingly important role in deep-submicrometer very large scale integrated technologies. Multiple design criteria are considered in interconnect design, such as delay, power, and bandwidth. In this paper, a repeater insertion methodology is presented for achieving t ..."
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Abstract—Interconnect plays an increasingly important role in deep-submicrometer very large scale integrated technologies. Multiple design criteria are considered in interconnect design, such as delay, power, and bandwidth. In this paper, a repeater insertion methodology is presented for achieving the minimum power in an RC interconnect while satisfying delay and bandwidth constraints. These constraints determine a design space for the number and size of the repeaters. The minimum power is shown to occur at the edge of the design space. With delay constraints, closed form solutions for the minimum power are developed, where the average error is 7 % as compared with SPICE. With bandwidth constraints, the minimum power can be achieved with minimum-sized repeaters. The effects of inductance on the delay, bandwidth, and power of an RLC interconnect with repeaters are also analyzed. By including inductance, the minimum interconnect power under a delay or bandwidth constraint decreases as compared with an RC interconnect. Index Terms—Bandwidth, delay, interconnect, low power,, repeater,.
Published by license under the OCP Science imprint, a member of the Old City Publishing Group Crosstalk Reduction by Voltage Scaling in Global VLSI Interconnects
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A Novel Low-Power Logic Circuit Design Scheme
"... Abstract—This brief proposes a novel low-power digital logic design scheme based on the energy exchange in the switched inductor–capacitor (SLC) circuit. It presents a design paradigm which in ideal case may lead to a circuit capable of performing logic operations with no switching losses. In tradit ..."
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Abstract—This brief proposes a novel low-power digital logic design scheme based on the energy exchange in the switched inductor–capacitor (SLC) circuit. It presents a design paradigm which in ideal case may lead to a circuit capable of performing logic operations with no switching losses. In traditional integrated circuit design, the energy is stored in the output load capacitor through a pull-up path (corresponding to storing a logic 1). When the output changes its logic value, this stored energy is dissipated through the pull down path to the ground. In order to reduce this switching energy dissipation each time the load capacitor is discharged, we store its energy in the magnetic field of the inductor in the proposed SLC architecture. Whenever the output load needs to be charged again, we transfer the energy back from the inductor to the load capacitor. This significantly reduces the switching energy. We illustrated the operation of the SLC architecture through SPICE simulation. A brief discussion of some practical considerations for this architecture is also presented. Index Terms—Buses, clock distribution tree, logic design, low power, switched inductor–capacitor (SLC) circuit. I.
II. THE BASIC TRAVELING-WAVE OSCILLATOR WITH WAVE REFLECTION AND REGENERATION
"... Abstract — We propose a novel traveling-wave oscillator (R 2 TWO) that uses reflection and regeneration of waves on a transmission line to generate multi-GHz square wave signals. We also propose a scalable, low-power, low-skew and low-jitter clock distribution network by tiling the basic R 2 TWOs in ..."
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Abstract — We propose a novel traveling-wave oscillator (R 2 TWO) that uses reflection and regeneration of waves on a transmission line to generate multi-GHz square wave signals. We also propose a scalable, low-power, low-skew and low-jitter clock distribution network by tiling the basic R 2 TWOs in a regular fashion. Measurement results of a TSMC 0.18µm CMOS test chip show that it can generate and distribute near full-swing 6.5GHz global clock signals with power saving of more than 75% (compared with a traditional ring oscillator). The measured jitter is less than 0.84ps, and the skew less than 1.3ps.
