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62
System Design using Kahn Process Networks: The Compaan/Laura Approach
- In Proceedings of "7th International Conference Design, Automation and Test in Europe (DATE'04
"... New emerging embedded system platforms in the realm of highthroughput multimedia, imaging, and signal processing will consist of multiple microprocessors and reconfigurable components. One of the major problems is how to program these platforms in a systematic and automated way so as to satisfy the ..."
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Cited by 65 (9 self)
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New emerging embedded system platforms in the realm of highthroughput multimedia, imaging, and signal processing will consist of multiple microprocessors and reconfigurable components. One of the major problems is how to program these platforms in a systematic and automated way so as to satisfy the performance need of applications executed on these platforms. In this paper, we present our system design approach as an efficient solution to this programming problem. We show how for an application written in Matlab, a Kahn Process Network specification can automatically be derived and systematically mapped onto a target platform composed of a microprocessor and an FPGA. Furthermore, we illustrate how the mapping approach is applied on a real-life example, namely an M-JPEG encoder. 1.
Analysis and Synthesis of Communication-Intensive Heterogeneous Real-Time Systems
- LINKÖPING STUDIES IN SCIENCE AND TECHNOLOGY, PH.D. DISSERTATION NO. 833
, 2003
"... EMBEDDED COMPUTER SYSTEMS are now everywhere: from alarm clocks to PDAs, from mobile phones to cars, almost all the devices we use are controlled by embedded computer systems. An important class of embedded computer systems is that of real-time systems, which have to fulfill strict timing requiremen ..."
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Cited by 33 (11 self)
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EMBEDDED COMPUTER SYSTEMS are now everywhere: from alarm clocks to PDAs, from mobile phones to cars, almost all the devices we use are controlled by embedded computer systems. An important class of embedded computer systems is that of real-time systems, which have to fulfill strict timing requirements. As realtime systems become more complex, they are often implemented using distributed heterogeneous architectures. The main objective of this thesis is to develop analysis and synthesis methods for communication-intensive heterogeneous hard real-time systems. The systems are heterogeneous not only in terms of platforms and communication protocols, but also in terms of scheduling policies. Regarding this last aspect, in this thesis we consider time-driven systems, event-driven systems, and a combination of both, called multi-cluster systems. The analysis takes into
ReSP: A non-intrusive transaction-level reflective MPSoC simulation platform for design space exploration
- in Proc. ASPDAC
, 2008
"... (ReSP), a transaction-level multiprocessor simulation platform based on the integration of SystemC and Python. ReSP exploits the concept of reflection, enabling the integration of SystemC components without source-code modifications and providing full observability of their internal state. ReSP offe ..."
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Cited by 16 (3 self)
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(ReSP), a transaction-level multiprocessor simulation platform based on the integration of SystemC and Python. ReSP exploits the concept of reflection, enabling the integration of SystemC components without source-code modifications and providing full observability of their internal state. ReSP offers fine-grained sim-ulation control and supports the evaluation of different hardware/ software configurations of a given application, enabling complete design space exploration. ReSP allows the evaluation of real-time applications on high-level hardware models since it provides the transparent emulation of POSIX-compliant Real-Time Operating Systems (RTOS) primitives. A number of experiments have been performed to validate ReSP and its capabilities, using a set of single- and multithreaded benchmarks, with both POSIX Threads (PThreads) and OpenMP programming styles. These experiments confirm that reflection introduces negligible (<1%) overhead when comparing ReSP to plain SystemC simulation. The results also show that ReSP can be successfully used to analyze and explore concurrent and reconfigurable applications even at very early development stages. In fact, the average error introduced by ReSP’s RTOS emulation is below 6.6 ± 5 % w.r.t. the same RTOS running on an instruction set simulator, while simulation speed increases by a factor of ten. Owing to the integration with a scripted language, simulation management is simplified, and experimental setup effort is considerably reduced. Index Terms—Design exploration, multiprocessor, Python, SystemC, system-level design, system-on-a-chip.
Schedulability-Driven Frame Packing for Multi-Cluster Distributed Embedded Systems
, 2003
"... We present an approach to frame packing for multi-cluster distributed embedded systems consisting of time-triggered and event-triggered clusters, interconnected via gateways. In our approach, the application messages are packed into frames such that the application is schedulable, thus the end-to-en ..."
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Cited by 14 (5 self)
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We present an approach to frame packing for multi-cluster distributed embedded systems consisting of time-triggered and event-triggered clusters, interconnected via gateways. In our approach, the application messages are packed into frames such that the application is schedulable, thus the end-to-end message communication constraints are satisfied. We have proposed a schedulability analysis for applications consisting of mixed event-triggered and time-triggered processes and messages, and a worst case queuing delay analysis for the gateways, responsible for routing inter-cluster traffic. Optimization heuristics for frame packing aiming at producing a schedulable system have been proposed. Extensive experiments and a real-life example show the efficiency of our frame-packing approach.
Performance Optimization of an FPGA-Based Configurable Multiprocessor for Matrix Operations
- IEEE Intern. Conf. Field-Programmable Techn
, 2003
"... Several driving forces have recently brought about significant advances in the field of configurable computing. They have also enabled parallel processing within a single field-programmable gate array (FPGA) chip. The ever-increasing complexity of application algorithms and the supercomputing crisis ..."
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Cited by 14 (4 self)
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Several driving forces have recently brought about significant advances in the field of configurable computing. They have also enabled parallel processing within a single field-programmable gate array (FPGA) chip. The ever-increasing complexity of application algorithms and the supercomputing crisis have made this new parallel-processing approach more important and pertinent. Its cost-effectiveness provides system designers with the greatest flexibility while imposing many challenges to current hardware and software codesign methodologies. This paper explores practical hardware and software design and implementation issues for FPGA-based configurable multiprocessors, based on the authors ' first-hand experience with a shared-memory implementation of parallel LU factorization for sparse block-diagonal-bordered (BDB) matrices. We also propose a new dynamic load balancing strategy for parallel LU factorization on our system. Performance results are included to prove the viability of this new multiprocessor design approach. 1.
Architectures for e-Textiles
, 2003
"... The huge advancement in the textiles industry and the accurate control on the mechanization process coupled with cost-e#ective manufacturing o#er an innovative environment for new electronic systems, namely electronic textiles. The abundance of fabrics in our regular life o#ers immense possibilities ..."
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Cited by 9 (0 self)
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The huge advancement in the textiles industry and the accurate control on the mechanization process coupled with cost-e#ective manufacturing o#er an innovative environment for new electronic systems, namely electronic textiles. The abundance of fabrics in our regular life o#ers immense possibilities for electronic integration both in wearable and large-scale applications. Augmenting this technology with a set of precepts and a simulation environment creates a new software/hardware architecture with widely useful implementations in wearable and large-area computational systems. The software environment acts as a functional modeling and testing platform, providing estimates of design metrics such as power consumption. The construction of an electronic textile (e-textile) hardware prototype, a large-scale acoustic beamformer, provides a basis for the simulator and o#ers experience in building these systems. The contributions of this research focus on defining the electronic textile architecture, creating a simulation environment, defining a networking scheme, and implementing hardware prototypes.
Profiling tools for FPGA-based embedded systems: survey and quantitative comparison
- Journal of Computers
, 2008
"... Abstract — Profiling tools are computer-aided design (CAD) tools that help in determining the computationally intensive portions in software. Embedded systems consist of hard-ware and software components that execute concurrently and efficiently to execute a specific task or application. Profiling t ..."
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Cited by 7 (0 self)
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Abstract — Profiling tools are computer-aided design (CAD) tools that help in determining the computationally intensive portions in software. Embedded systems consist of hard-ware and software components that execute concurrently and efficiently to execute a specific task or application. Profiling tools are used by embedded system designers to choose computationally intensive functions for hardware implementation and acceleration. In this paper we review and compare various existing profiling tools for FPGA-based embedded systems. We then describe Airwolf, an FPGA-based profiling tool. We present a quantitative comparison of Airwolf and a well known software-based profiling tool, GNU gprof. Four software benchmarks were used to obtain profiling results using Airwolf and gprof. We show that Airwolf provides up to 66.2 % improvement in accuracy of profiled results and reduces the run time performance overhead, caused by software-based profiling tools, by up to 41.3%. The results show that Airwolf provides accurate profiling results with minimal overhead and it can help the designers of FPGA-based embedded systems in identifying the computationally intensive portions of software code for hardware implementation and acceleration.
Design Optimization of Multi-Cluster Embedded Systems for Real-Time Applications
- in Proceedings of Design, Automation and Test in Europe Conference
, 2004
"... We present an approach to design optimization of multi-cluster embedded systems consisting of time-triggered and event-triggered clusters, interconnected via gateways. In this paper, we address design problems which are characteristic to multi-clusters: partitioning of the system functionality into ..."
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Cited by 6 (4 self)
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We present an approach to design optimization of multi-cluster embedded systems consisting of time-triggered and event-triggered clusters, interconnected via gateways. In this paper, we address design problems which are characteristic to multi-clusters: partitioning of the system functionality into time-triggered and event-triggered domains, process mapping, and the optimization of parameters corresponding to the communication protocol. We present several heuristics for solving these problems. Our heuristics are able to find schedulable implementations under limited resources, achieving an efficient utilization of the system. The developed algorithms are evaluated using extensive experiments and a real-life example. 1.
Implementation of Hybrid Control for Motor Drives
- IEEE Trans. Ind. Electron
, 2007
"... Abstract—This paper presents the implementation of a hybrid-control strategy applied to a permanent-magnet synchronous-motor (PMSM) drive. Hybrid control is a general approach for control of a switching-based hybrid system (HS). This class of HS includes a continuous process controlled by a discrete ..."
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Cited by 5 (2 self)
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Abstract—This paper presents the implementation of a hybrid-control strategy applied to a permanent-magnet synchronous-motor (PMSM) drive. Hybrid control is a general approach for control of a switching-based hybrid system (HS). This class of HS includes a continuous process controlled by a discrete controller with a finite number of states. In the case of ac motor drives, in contrast to conventional vector control like proportional–integral control or predictive control, where the inverter is not taken into account by the controller, hybrid control integrates the inverter model and considers the state of the inverter as a control variable. It allows to obtain faster torque dynamics than vector-control algorithms. The hybrid control algorithm requires both com-puting velocity for real-time implementation and code flexibility for management of low-performance functions and analog–digital interfaces. Codesign appears as a promising methodology for par-titioning hybrid-control algorithm between software (flexible) and hardware (velocity) while taking care of overall time constrains. In this paper, the implementation of hybrid-control algorithm for a PMSM drive is performed through a codesign approach on an Excalibur board, embedding a CPU-core (Nios-2 by Altera) in-side an APEX20KE200EFC484-2X field-programmable gate ar-ray. The partitioning of software and hardware parts is explained. Experimental results show the effectiveness of the implementation. Performances, advantages, and limitations are discussed. Index Terms—AC motor drives, control, dynamic hybrid system (HS), field-programmable gate array (FPGA), hardware–software codesign. I.
