• Integrated FIFOs and Dedicated DMA Channels – USB 2.0 Full Speed (12 Mbits per second) Device Port • On-chip Transceiver, 2 Kbyte Configurable Integrated FIFOs • Bus Matrix

Abstract—In this paper we present a static performance estimation technique of on-chip bus architectures. The proposed technique requires the static scheduling of function blocks of a task to analyze bus conflicts caused by simultaneous accesses from processing elements to which function blocks

to self-heating of on-chip buses increases as technology scales, thus motivating the need of finding solutions to mitigate this effect. Based on the theoretical analysis, we propose an irredundant bus encoding scheme for on-chip buses to tackle the thermal issue. Simulation results show that our encoding

Abstract- In this paper, we employ a monitor-based approach for on-chip bus (OCB) compliance test. To describe the OCB protocols, we propose a FSM model, which can help to extract the necessary properties systematically and verify the data part of a bus transfer efficiently. To demonstrate our

Abstract — As more and more IP cores are integrated into an SOC design, the communication flow between IP cores has increased drastically and the efficiency of the on-chip bus has become a dominant factor for the performance of a system. The on-chip bus design can be divided into two parts, namely

Abstract- In this paper, we employ a monitor-based approach for on-chip bus (OCB) compliance test. To describe the OCB protocols, we propose a FSM model, which can help to extract the necessary properties systematically and verify the data part of a bus transfer efficiently. To demonstrate our

, and senseamplifiers we retain high performance. A testchip built in a 1.8V 0.18-#m technology consumed # 1pJ/bit for a 10mm bus at 1GHz, a power savings over full-swing signaling of up to 10x, and demonstrated amplifier input offset voltages of under 100mV.

, the generation rate and the size of real time system traces are so huge such that a mechanism for system tracing that can reduce trace size efficiently is needed. In this paper, we purpose an on-chip bus signals tracer for SoC’s. This bus tracer can perform a cycle-accurate or successive trace collection

Abstract: Modern VLSI technology makes it both feasible and economical to integrate a complex system on a single chip. These modules often require different data transfer speeds and parallel transmission capability. A conventional bus structure might not be adequate for these demands because

The latest improvements in the technology of digital devices allow designers to build whole systems on a single silicon chip. New problems arise in this context, one of them being the complexity of interconnections. Optimizing interfaces has become a tedious design step. Another issue is the power