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Table 3: Some selected systolic Array Computers

in unknown title
by unknown authors

Table 2: Comparison of various systolic arrays for 1-D DHT

in unknown title
by unknown authors
"... In PAGE 2: ... On the other hand, in [3] N CORDICs and in [4] N multipliers are needed. Table2 illustrates the performance comparison of various systolic implementations of 1-D DHT. From Table 1 it is obvious that 7/16 of operations in PE1s are actually simple data transfer operations sout G06 sin.... ..."

Table 1. Systolic array LZ-compress implementation on emulation platforms.

in unknown title
by unknown authors
"... In PAGE 5: ... The decompression of LZ implementa- tion in Figure 4 is simply a memo- ry access, and thus the extra cost for error detection can be smaller than for other implementations of LZ-based algorithms. Table1 shows implementation results of our proposed scheme in the Quickturn and Wildforce emu- lation testbeds. The decoder shares the dictionary with the encoder, and the checker block is implemented by using an extra PE.... ..."

Table 1. Processing time for a cluster of workstations and the systolic array.

in Reconfigurable Systems for Sequence Alignment and for General Dynamic Programming §
by Ricardo P. Jacobi, Mauricio Ayala-rincón, Luis G. A. Carvalho, Carlos H. Llanos, Reiner W. Hartenstein, Fachbereich Informatik Technische Universität Kaiserslautern

Table 1. FSBM systolic structures. Architecture #PE T

in A New Efficient VLSI Architecture for Full Search Block Matching Motion Estimation
by Nuno Roma, Leonel Sousa
"... In PAGE 4: ... For comparison purposes, it was also considered the limit situation corresponding to a processor array with a single PE, which was designated by SinglePE architecture. It is worth noting that, in practice, the real values of T can be significantly greater than those presented in Table1 . Frequently, extra clock cycles are necessary to fill the pipeline and dummy results are often computed to preserve a regular data flow.... In PAGE 4: ... Frequently, extra clock cycles are necessary to fill the pipeline and dummy results are often computed to preserve a regular data flow. The circuit area (A*) and the processing time (T*) of the considered architectures were estimated by parameterizing the set of expressions presented in Table1 in terms of k = p/N. The obtained results are presented in Figure 2 and Figure 3, respectively, using logarithmic scales to accommodate the large range of values.... ..."
Cited by 1

Table 6: Variants of Systolic Arrays for Convolution III For the systolic array 7d with processor mapping = ( ?1 1) the transport of the values of variable x can again be implemented in two ways just as for version 5d.

in A Model for Systolic Parallelization of Multiple Loop Programs
by Friedrich Wichmann

Table 1 shows the performance comparison of DCT architectures using systolic array struc-

in A Unified Systolic Array for Fast Computation of the DCT/DST/DHT
by Sung Bum Pan, Rae-Hong Park, Prof Rae-hong Park
"... In PAGE 14: ... 3 Proposed 2-D systolic array for computation of the eight-point IDCT: #28a#29 functional de#0Cnition of the PE, #28b#29 architecture. Table Captions Table1 Performance comparison of several systolic array architectures for computation of the N-point DCT.... ..."

TABLE III FIXED BLOCK SIZE RESULTS FOR SYSTOLIC ARRAY PROCESSORS (BEST PERFORMANCE IN BOLD)

in Serial and Parallel FPGA-based Variable Block Size Motion Estimation Processors
by Brian M. H. Li, Philip H. W. Leong

Table 1: Some 3D algorithms for which processor-time-minimal systolic arrays are known.

in Processor-Time-Optimal Systolic Arrays
by Peter Cappello, Ömer Egecioglu, Chris Scheiman
"... In PAGE 2: ... Processor-time-minimal schedules for various fundamental problems have been proposed in the literature: Scheiman and Cappello [8, 5, 47, 44] examine the dag family for matrix product; Louka and Tchuente [33] examine the dag family for Gauss-Jordan elimination; Scheiman and Cappello [45, 46] examine the dag family for transitive closure; Benaini and Robert [3, 2] examine the dag families for the algebraic path problem and Gaussian elimination. Each of the algorithms listed in Table1 has the property that, in its dag representation, every node is on a longest path: Its free schedule is its only time-minimal schedule. A processor lower bound for achieving it is thus a processor lower bound for achieving maximum parallelism with the algorithm.... ..."

Table 1: Some 3D algorithms for which processor-time-minimal systolic arrays are known.

in Processor-Time-Optimal Systolic Arrays
by Peter Cappello, Ömer Egecioglu, Chris Scheiman
"... In PAGE 2: ... Processor-time-minimal schedules for various fundamental problems have been proposed in the literature: Scheiman and Cappello #5B8,5,47,44#5D examine the dag family for matrix product; Louka and Tchuente #5B33#5D examine the dag family for Gauss-Jordan elimination; Scheiman and Cappello #5B45,46#5D examine the dag family for transitive closure; Benaini and Robert #5B3,2#5D examine the dag families for the algebraic path problem and Gaussian elimination. Each of the algorithms listed in Table1 has the property that, in its dag representation, every node is on a longest path: Its free schedule is its only time-minimal schedule. A processor lower bound for achieving it is thus a processor lower bound for achieving maximum parallelism with the algorithm.... ..."
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