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847
Software pipelining: An effective scheduling technique for VLIW machines
, 1988
"... This paper shows that software pipelining is an effective and viable scheduling technique for VLIW processors. In software pipelining, iterations of a loop in the source program are continuously initiated at constant intervals, before the preceding iterations complete. The advantage of software pipe ..."
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Cited by 581 (3 self)
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number of iterations. Hierarchical reduction comple-ments the software pipelining technique, permitting a consis-tent performance improvement be obtained. The techniques proposed have been validated by an im-plementation of a compiler for Warp, a systolic array consist-ing of 10 VLIW processors
Some efficient solutions to the affine scheduling problem -- Part I One-dimensional Time
, 1996
"... Programs and systems of recurrence equations may be represented as sets of actions which are to be executed subject to precedence constraints. In many cases, actions may be labelled by integral vectors in some iteration domain, and precedence constraints may be described by affine relations. A s ..."
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Cited by 266 (22 self)
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schedule for such a program is a function which assigns an execution date to each action. Knowledge of such a schedule allows one to estimate the intrinsic degree of parallelism of the program and to compile a parallel version for multiprocessor architectures or systolic arrays. This paper deals
Programmable Systolic Arrays
- Brown University
, 1991
"... This paper presents the New Systolic Language as a general solution to the problem systolic programming. The language provides a simple programming interface for systolic algorithms suitable for di erent hardware platforms and software simulators. The New Systolic Language hides the details and pote ..."
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Cited by 20 (7 self)
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This paper presents the New Systolic Language as a general solution to the problem systolic programming. The language provides a simple programming interface for systolic algorithms suitable for di erent hardware platforms and software simulators. The New Systolic Language hides the details
General-purpose systolic arrays
- IEEE Computer
, 1993
"... effectively exploit massive parallelism in computationally intensive applications. With advances in VLSI, WSI, and FPGA technologies, they have progressed from fixedfunction to generalpurpose architectures. hen Sun Microsystems introduced its first workstation, the company could not have imagined ho ..."
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Cited by 13 (0 self)
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effectively exploit massive parallelism in computationally intensive applications. With advances in VLSI, WSI, and FPGA technologies, they have progressed from fixedfunction to generalpurpose architectures. hen Sun Microsystems introduced its first workstation, the company could not have imagined how quickly workstations would revolutionize computing. The idea of a community of engineers, scientists, or researchers time-sharing on a single mainframe computer could hardly have become ancient any more quickly. The almost instant wide acceptance of workstations
BOUNDED BROADCAST IN SYSTOLIC ARRAYS
, 2006
"... Much work has been done on the problem of synthesizing a processor array from a system of recurrence equations. Some researchers limit communication to nearest neighbors in the array; others use broadcast. In many cases, neither of the above approaches result in an optimal execution time. In this pa ..."
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Cited by 1 (0 self)
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those reported previously. In general, the technique can be used to design bounded broadcast systolic arrays for algorithms whose implementation can benefit from broadcasting. Keywords: all-pairs shortest distance, broadcast, data dependence, parallel computation, recurrence equation, systolic array
systolic arrays on FPGAs
"... RNA structure prediction, or folding, is a computeintensive task that lies at the core of several search applications in bioinformatics. We begin to address the need for high-throughput RNA folding by accelerating the Nussinov folding algorithm using a 2D systolic array architecture. We adapt classi ..."
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RNA structure prediction, or folding, is a computeintensive task that lies at the core of several search applications in bioinformatics. We begin to address the need for high-throughput RNA folding by accelerating the Nussinov folding algorithm using a 2D systolic array architecture. We adapt
Systolic Arrays for Image Processing
"... Recent advances in VLSI technology offer to the user to fabricate thousands of switching elements on a single chip. Computation power can be significantly increased by parallel processing of the algorithms mapped and designed in VLSI technology for applications that require large computational power ..."
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power. The major applications in image processing systems may be divided into few categories; pre-processing, coding, compression, restoration, segmentation, representation, description and interpretation. Introducing the systolic arrays into the area of image processing can significantly improve speed
On Laguerre Expansions and Systolic Arrays
- Computers and Electrical Engineering. RST n I RST n I I O O O
"... Discrete-time Laguerre sequences are effective for representing sequences in the form of orthogonal expansions. The main objective of this communication is to propose a systolicarray implementaion for finite-duration Laguerre expansions. Supported by a fellowship provided through the NASA Microel ..."
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Cited by 1 (1 self)
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of Laguerre expansions, although the Laguerre expansion of a discrete sequence can be represented as a network. Thus the purpose of this paper is to propose a systolic array implementation for Laguerre expansions. 2 Laguerre Expansions Given a sequence x(n), its Laguerre expansion is defined as [4],[5] x
Derivation of Systolic Convolution Arrays
"... We show how the refinement calculus, combined with the action system formalism gives a stepwise refinement method for deriving parallel convolution algorithms that model systolic computation. We inspect how different architectural designs influence the derivation process. The action systems framewor ..."
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We show how the refinement calculus, combined with the action system formalism gives a stepwise refinement method for deriving parallel convolution algorithms that model systolic computation. We inspect how different architectural designs influence the derivation process. The action systems
Results 1 - 10
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847