Results 1 - 10 of 2,079

Subthreshold Voltage High-k CMOS Devices Have Lowest Energy and High Process Tolerance

by Muralidharan Venkatasubramanian, Vishwani D. Agrawal
"... Abstract — Evolving nanometer CMOS technologies provide low power, high performance and higher levels of integration but suffer from increased subthreshold leakage and excessive process variation. The present work examines the 45nm bulk and high-k technologies. We evaluate the performance of a 32-bi ..."
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, subthreshold voltage operation, nanometer CMOS devices, high-k CMOS technology, process variation.

Design of an energy-efficient 32-bit adder operating at subthreshold voltages in 45-nm CMOS

by Anh T. Tran, Bevan M. Baas - in Proc. 3rd International Conference on Communications and Electronics , 2011
"... Abstract—Low-power circuits have been quickly increasing their importance due to the high cost in design of cooling systems with complex chip packaging techniques, and also due to the low energy consumption requirement of portable devices powered by a limited battery capacity. This paper presents th ..."
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the design of a low-power 32-bit adder that is a basic functional unit in most computational platforms. Its energy efficiency is highly achieved while operating in the subthreshold regime. Simulation results in 45-nm PTM CMOS show the adder consumes only 22 fJ per computation at 0.2 V with maximum operating

Optimal Supply and Threshold Scaling for Subthreshold CMOS Circuits

by Alice Wang And, Alice Wang, Anantha P. Ch - IEEE Symposium on VLSI , 2002
"... With technology scaling, power supply and threshold voltage continue to decrease to satisfy high performance and low power requirements. In the past, subthreshold CMOS circuits have been inadequate for high performance applications, but have been used in applications that require ultra low power dis ..."
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With technology scaling, power supply and threshold voltage continue to decrease to satisfy high performance and low power requirements. In the past, subthreshold CMOS circuits have been inadequate for high performance applications, but have been used in applications that require ultra low power

Internet Devices in 45 nm High-k Metal Gate CMOS

by Gianfranco Gerosa, Steve Curtis, Bo Jiang, Feroze Merchant, Binta Patel, Mohammed H. Taufique, Haytham Samarchi
"... Abstract—This paper describes a low power Intel Architecture (IA) processor specifically designed for Mobile Internet Devices (MID) with performance similar to mainstream Ultra-Mobile PCs. The design relies on high residency in a new low-power state in order to keep average power and idle power belo ..."
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Abstract—This paper describes a low power Intel Architecture (IA) processor specifically designed for Mobile Internet Devices (MID) with performance similar to mainstream Ultra-Mobile PCs. The design relies on high residency in a new low-power state in order to keep average power and idle power

Influence of High-k Gate Dielectric on Nanoscale DG-MOSFET

by S. K. Mohapatra, K. P. Pradhan, P. K. Sahu
"... Influence of dielectric materials as gate oxide on various short channel device parameters using a 2-D device simulator has been studied in this paper. It is found that the use of high-k dielectrics directly on the silicon wafer would degrade the performance. This degradation is mainly due to the fr ..."
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Influence of dielectric materials as gate oxide on various short channel device parameters using a 2-D device simulator has been studied in this paper. It is found that the use of high-k dielectrics directly on the silicon wafer would degrade the performance. This degradation is mainly due

Full-Chip Subthreshold Leakage Power Prediction and Reduction Techniques for Sub-0.18-μm CMOS

by Siva Narendra, Vivek De, Shekhar Borkar, Dimitri A. Antoniadis, Anantha P. Chandrakasan, Anantha P. Ch - IEEE Journal of Solid-State Circuits , 2004
"... The driving force for the semiconductor industry growth has been the elegant scaling nature of CMOS technology. In future CMOS technology generations, supply and threshold voltages will have to continually scale to sustain performance increase, control switching power dissipation, and maintain relia ..."
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measurements in 0.18- m and 0.13- m are presented. Measurements also demonstrate reduction in threshold voltage variation for stacked devices compared to nonstack devices. Comparison of the stack effect to the use of high threshold voltage or longer channel length devices for subthreshold leakage reduction

Degradation in MOSFET Multi-Stack High-k Gate Dielectrics Due to Hot Carrier and Constant Voltage Stress

by Zeynep Çelik-butler, M. Shahriar Rahman
"... Hafnium based materials are the leading high dielectric constant (high-k) candidates to replace conventional SiO2 and SiON as the gate dielectric in complementary metal-oxide-semiconductor (CMOS) devices for sub-45nm technology nodes. To explain the low frequency noise behavior in these gate dielect ..."
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Hafnium based materials are the leading high dielectric constant (high-k) candidates to replace conventional SiO2 and SiON as the gate dielectric in complementary metal-oxide-semiconductor (CMOS) devices for sub-45nm technology nodes. To explain the low frequency noise behavior in these gate

Device-Circuit Interactions in Extremely Low Voltage CMOS Designs (Invited)

by Hiroshi Fuketa, Tadashi Yasufuku, Satoshi Iida, Makoto Takamiya, Masahiro Nomura
"... In this paper, energy and minimum operating voltage (VDDmin) are investigated for extremely-low-voltage CMOS logic designs. The dependences of energy and VDDmin on device parameters, such as threshold voltage, subthreshold swing parameter, and DIBL coefficient, are examined based on simulations and ..."
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In this paper, energy and minimum operating voltage (VDDmin) are investigated for extremely-low-voltage CMOS logic designs. The dependences of energy and VDDmin on device parameters, such as threshold voltage, subthreshold swing parameter, and DIBL coefficient, are examined based on simulations

In0.7Ga0.3As tunneling field-effect-transistors with LaAlO3 and ZrO2 high-k dielectrics

by Fei Xue, Han Zhao, Yen-ting Chen, Yanzhen Wang, Fei Zhou, Jack C. Lee
"... As scaling of silicon complementary metal-oxide-semiconductor (CMOS) device approaches its limit, new materials and device structures are desirable to further improve the device performance and to reduce power consumption. For conventional MOSFETs, however, to reduce the supply voltage and maintain ..."
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As scaling of silicon complementary metal-oxide-semiconductor (CMOS) device approaches its limit, new materials and device structures are desirable to further improve the device performance and to reduce power consumption. For conventional MOSFETs, however, to reduce the supply voltage and maintain

Impacts of NBTI/PBTI and contact resistance on power-gated SRAM wih high-k metal-gate devices

by Hao-i Yang, Student Member, Wei Hwang, Ching-te Chuang - IEEE Trans. Very Large Scale Integr. (VLSI) Syst
"... Abstract—The threshold voltage drifts induced by neg-ative bias temperature instability (NBTI) and positive bias tem-perature instability (PBTI) weaken PFETs and high-k metal-gate NFETs, respectively. These long-term drifts degrade SRAM cell stability, margin, and performance, and may lead to func ..."
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Abstract—The threshold voltage drifts induced by neg-ative bias temperature instability (NBTI) and positive bias tem-perature instability (PBTI) weaken PFETs and high-k metal-gate NFETs, respectively. These long-term drifts degrade SRAM cell stability, margin, and performance, and may lead
Results 1 - 10 of 2,079