Results 1 - 10 of 293

Transconductors in Subthreshold CMOS

by Paul M. Furth, Andreas G. Andreou , 1995
"... Four schemes for linearizing the transconductance of the basic di#erential pair in subthreshold CMOS are examined. They are: source degeneration via #1# diode-connected transistors, #2# a single di#usor and #3# symmetric di#usors, and #4# multiple asymmetric di#erential pairs. We derive equations fo ..."
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Four schemes for linearizing the transconductance of the basic di#erential pair in subthreshold CMOS are examined. They are: source degeneration via #1# diode-connected transistors, #2# a single di#usor and #3# symmetric di#usors, and #4# multiple asymmetric di#erential pairs. We derive equations

Subthreshold behavior and phenomenological impedance of the squid giant

by A. Mauro, F. Conti, F. Dodge, R. Schor , 1970
"... ABSTRACT The oscillatory behavior of the cephalopod giant axons in response to an applied current has been established by previous investigators. In the study reported here the relationship between the familiar "RC " electrotonic response and the oscillatory behavior is examined experiment ..."
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the three currents, in general, have nonzero resting values and two currents, the "Na " system and the "K " system, are controlled by voltage-dependent time-variant conductances, the subthreshold behavior of the squid axon in the small-signal range can be looked upon as arising from

Linearized Differential Transconductors in Subthreshold CMOS

by Subthreshold Cmos, Paul M. Furth, Andreas G. Andreou , 1995
"... Three schemes for linearizing the transconductance of the basic differential pair in subthreshold CMOS are examined: 1) multiple asymmetric differential pairs, 2) source degeneration via symmetric diffusors, and 3) source degeneration via a single diffusor. Using a maximally flat optimizing criterio ..."
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Three schemes for linearizing the transconductance of the basic differential pair in subthreshold CMOS are examined: 1) multiple asymmetric differential pairs, 2) source degeneration via symmetric diffusors, and 3) source degeneration via a single diffusor. Using a maximally flat optimizing

Soft Error Immunity of Subthreshold SRAM

by Masanori Hashimoto
"... Abstract—This paper discusses soft error immunity of sub-threshold SRAM presenting neutron- and alpha-induced soft error rates (SER) in 65-nm 10T SRAM over a wide range of supply voltages from 1.0 to 0.3 V. The results show that the neutron-induced SER at 0.3 V is 7.8 times as high as that at 1.0 V. ..."
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Abstract—This paper discusses soft error immunity of sub-threshold SRAM presenting neutron- and alpha-induced soft error rates (SER) in 65-nm 10T SRAM over a wide range of supply voltages from 1.0 to 0.3 V. The results show that the neutron-induced SER at 0.3 V is 7.8 times as high as that at 1.0 V

Minimum Energy CMOS Design with Dual Subthreshold Supply and Multiple Logic-Level Gates

by Kyungseok Kim, Vishwani D. Agrawal
"... Abstract—This paper presents a method for minimum energy digital CMOS circuit design using dual subthreshold supply voltages. Stringent energy budget and moderate speed requirements of some ultra low power systems may not be best satisfied just by scaling a single supply voltage. Optimized circuits ..."
Abstract - Cited by 8 (6 self) - Add to MetaCart
with dual supply voltages provide an opportunity to resolve these demands. The delay penalty of a traditional level converter is unacceptably high when the voltages are in the subthreshold range. In the present work level converters are not used and special multiple logic-level gates are used only when

Subthreshold voltage noise of rat neocortical pyramidal neurones

by Gilad A. Jacobson, Kamran Diba, Anat Yaron-jakoubovitch, Yasmin Oz, Christof Koch, Idan Segev, Yosef Yarom - J Physiol , 2005
"... Neurones are noisy elements. Noise arises from both intrinsic and extrinsic sources, and manifests itself as fluctuations in the membrane potential. These fluctuations limit the accuracy of a neurone’s output but have also been suggested to play a computational role. We present a detailed study of t ..."
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model reproduces qualitatively these data. Our results imply that ion channel noise contributes significantly to membrane voltage fluctuations at the subthreshold voltage range, and that Na + conductance plays a key role in determining the amplitude of this noise by acting as a voltage

Stack Sizing for Optimal Current Drivability in Subthreshold Circuits

by John Keane, Hanyong Eom, Tae-hyoung Kim, Sachin Sapatnekar, Chris Kim
"... Abstract—Subthreshold circuit designs have been demonstrated to be a successful alternative when ultra-low power consumption is paramount. However, the characteristics of MOS transistors in the subthreshold region are significantly different from those in stronginversion. This presents new challenge ..."
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of transistors in a stack, both in relation to other transistors in the stack, and to a single device with equivalent current drivability. Simulation results show that our framework provides a performance benefit ranging up to more than 10 % in certain critical paths. Index Terms—Subthreshold logic, logical

Cortical point-spread function and long-range lateral interactions revealed by real-time optical imaging of macaque monkey primary visual cortex

by Amiram Grinvald, Edmund E. Lieke, A Ron D. Frostig, Rina Hildesheim - Journal of Neuroscience , 1994
"... Processing of retinal images is carried out in the myriad dendritic arborizations of cortical neurons. Such processing involves complex dendritic integration of numerous inputs, and the subsequent output is transmitted to multiple targets by extensive axonal arbors. Thus far, details of this intrica ..."
Abstract - Cited by 126 (3 self) - Add to MetaCart
-tential of a population of neuronal elements, including the often elusive subthreshold synaptic potentials that impinge on the extensive arborization of cortical cells. By using small visual stimuli with sharp borders and real-time imaging of cortical responses, we found that shortly

A Subthreshold SCL Based Pipelined Encoder for

by Ultra-low Power, Mohammad Beikahmadi, Armin Tajalli, Yusuf Leblebici
"... Abstract- The subthreshold MOS source-coupled logic (STSCL) technique is of great interest for designing ultra low power circuits. In this paper we discuss the design of a pipelined encoder for an 8-bit folding and interpolating (F&I) analog-to-digital (ADC) data converter using this technique. ..."
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Abstract- The subthreshold MOS source-coupled logic (STSCL) technique is of great interest for designing ultra low power circuits. In this paper we discuss the design of a pipelined encoder for an 8-bit folding and interpolating (F&I) analog-to-digital (ADC) data converter using this technique

Optimal Supply and Threshold Scaling for Subthreshold CMOS Circuits

by Alice Wang And, Alice Wang, Anantha P. Ch - IEEE Symposium on VLSI , 2002
"... With technology scaling, power supply and threshold voltage continue to decrease to satisfy high performance and low power requirements. In the past, subthreshold CMOS circuits have been inadequate for high performance applications, but have been used in applications that require ultra low power dis ..."
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With technology scaling, power supply and threshold voltage continue to decrease to satisfy high performance and low power requirements. In the past, subthreshold CMOS circuits have been inadequate for high performance applications, but have been used in applications that require ultra low power
Results 1 - 10 of 293