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474
Minimum Energy CMOS Design with Dual Subthreshold Supply and Multiple Logic-Level Gates
"... Abstract—This paper presents a method for minimum energy digital CMOS circuit design using dual subthreshold supply voltages. Stringent energy budget and moderate speed requirements of some ultra low power systems may not be best satisfied just by scaling a single supply voltage. Optimized circuits ..."
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Cited by 8 (6 self)
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with dual supply voltages provide an opportunity to resolve these demands. The delay penalty of a traditional level converter is unacceptably high when the voltages are in the subthreshold range. In the present work level converters are not used and special multiple logic-level gates are used only when
Long Short-term Memory
, 1995
"... "Recurrent backprop" for learning to store information over extended time intervals takes too long. The main reason is insufficient, decaying error back flow. We briefly review Hochreiter's 1991 analysis of this problem. Then we overcome it by introducing a novel, efficient method c ..."
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Cited by 454 (58 self)
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called "Long Short Term Memory" (LSTM). LSTM can learn to bridge minimal time lags in excess of 1000 time steps by enforcing constant error flow through internal states of special units. Multiplicative gate units learn to open and close access to constant error flow. LSTM's update
Petrify: a tool for manipulating concurrent specifications and . . .
"... Petrify is a tool for (1) manipulating concurrent specifications and (2) synthesis and optimization of asynchronous control circuits. Given a Petri Net (PN), a Signal Transition Graph (STG), or a Transition System (TS) 1 it (1) generates another PN or STG which is simpler than the original descripti ..."
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Cited by 219 (34 self)
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State Coding problem. State assignment is coupled with logic minimization and speed-independent technology mapping to a target library. The final net-list is guaranteed to be speed-independent, i.e., hazard-free under any distribution of gate delays and multiple input changes satisfying the initial
Automatic Partitioner for Behavior Level Distributed Logic Simulation
"... Abstract. As the complexity of circuit design increases, verification through simulation has become a bottleneck of the IC design process. Distributed parallel simulation is one way to solving the problem. In order to distribute the simulation workload to multiple processors, the design must be care ..."
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be carefully partitioned first. While most previous work focus on gate level partitioning, our work extends a previously implemented Verilog gate-level partitioner to support RTL and behavior level partitioning. Techniques to partition special constructs specific to these levels, such as global access
A Conservative Adaptive Projection Method for the Variable Density Incompressible Navier–Stokes Equations
- JOURNAL OF COMPUTATIONAL PHYSICS 142, 1–46 (1998)
, 1998
"... In this paper we present a method for solving the equations governing time-dependent, variable density incompressible flow in two or three dimensions on an adaptive hierarchy of grids. The method is based on a projection formulation in which we first solve advection–diffusion equations to predict in ..."
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Cited by 131 (28 self)
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in both space and time. The integration algorithm on the grid hierarchy is a recursive procedure in which coarse grids are advanced in time, fine grids are advanced multiple steps to reach the same time as the coarse grids and the data at different levels are then synchronized. The single grid algorithm
On Bifunctional Polymorphic Gates Controlled by a Special Signal
"... Abstract:- Polymorphic digital circuits are circuits composed of polymorphic (multifunctional) as well as ordinary gates. In addition to its standard logic function (such as NAND), a polymorphic gate exhibits another logic function which is activated under a specific condition, for example, when Vdd ..."
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Vdd, temperature, illumination or a special signal reaches a certain level. This paper describes existing polymorphic gates and their features, benefits and limits and discusses special class of polymorphic gates – bifunctional polymorphic gates controlled by a special signal. These gates seem
Optimal synthesis of multiple output Boolean functions using a set of quantum gates by symbolic reachability analysis
- IEEE Trans. on CAD of Integrated Circuits and Systems
, 2006
"... Abstract—This paper proposes an approach to optimally synthesize quantum circuits by symbolic reachability analysis, where the primary inputs and outputs are basis binary and the internal signals can be nonbinary in a multiple-valued domain. The authors present an optimal synthesis method to minimiz ..."
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Cited by 51 (5 self)
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to minimize quantum cost and some speedup methods with nonoptimal quantum cost. The methods here are applicable to small reversible functions. Unlike previous works that use permutative reversible gates, a lower level library that includes nonpermutative quantum gates is used here. The proposed approach
Design and Reliability Analysis of Multiple Valued Logic Gates using Carbon Nanotube FETs
- in IEEE/ACM International Symposium on Nanoscale Architectures
, 2012
"... Abstract—With emerging nanometric technologies, multiple valued logic (MVL) circuits have attracted significant attention due to advantages in information density and operating speed. In this paper, a pseudo complementary MVL design is initially proposed for implementations using carbon nanotube fie ..."
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Cited by 1 (0 self)
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structures and their operation, so it yields a more realistic framework than a logic-level analysis of reliability. To achieve scalability, stochastic computational models are developed to accurately and efficiently analyze MVL gates; the extension of these models to circuits is briefly discussed. Keywords
Materials for an exploratory theory of the network society.
- The British Journal of Sociology
, 2000
"... ABSTRACT This article aims at proposing some elements for a grounded theor y of the network society. The network society is the social structure characteristic of the Information Age, as tentatively identi ed by empirical, cross-cultural investigation. It permeates most societies in the world, in v ..."
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Cited by 122 (0 self)
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mediations, imposes its structural determination to relationships of production. More speci cally, global nancial markets and their management networks constitute an automated network, governed by interactions between its multiple nodes, propelled by a combination of market logic, information turbulences
Cell multiprocessor communication network: Built for speed
- IEEE Micro
, 2006
"... Over the past decade, high-performance computing has ridden the wave of commodity computing, building clusterbased parallel computers that leverage the tremendous growth in processor performance fueled by the commercial world. As this pace slows, processor designers face complex problems in their ef ..."
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Cited by 108 (0 self)
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in their efforts to increase gate density, reduce power consumption, and design efficient memory hierarchies. Processor developers are looking for solutions that can keep up with the scientific and industrial communities’ insatiable demand for computing capability and that also have a sustainable market outside
Results 1 - 10
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474
