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Parallel Processor Configuration Design
- IEEE Transactions on Computers
, 2000
"... this paper, we examine a computer configuration design problem that has implications for the leasing of networked computer time ..."
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this paper, we examine a computer configuration design problem that has implications for the leasing of networked computer time
Application-level Performance Prediction Across Multi-Core Processor Configurations
"... Multiple cores, simultaneous multi-threading, and onchip caches are important processor configurations for ..."
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Multiple cores, simultaneous multi-threading, and onchip caches are important processor configurations for
Area And Performance Analysis Of Processor Configurations With Scaling Of Technology
, 1994
"... As integrated circuit density increases, computer architects face the interesting problem of how best to utilize the available die size given cost and performance constraints. Traditionally, area partitioning and floor-planning have been done in an ad hoc fashion based on intuition and experience of ..."
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Cited by 4 (0 self)
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of the designers. This paper proposes a systematic methodology for correlating area and performance as the designer increases the transistor count of a given sub-unit. Specifically, we investigate the performance of three possible processor configurations, and present performance results as the mimimun feature
Model Checking Reconfigurable Processor Configurations for Safety Properties
"... Reconfigurable processors pose unique problems for program safety because of their use of computational approaches that are difficult to integrate into traditional program analyses. The combination of proof-carrying code for verification of standard processor machine code and model-checking for a ..."
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Reconfigurable processors pose unique problems for program safety because of their use of computational approaches that are difficult to integrate into traditional program analyses. The combination of proof-carrying code for verification of standard processor machine code and model
Applying a Mutation-Based Genetic Algorithm to Processor Configuration Problems
, 1996
"... The Processor Configuration Problem (PCP) is a Constraint Optimization Problem. The task is to link up a finite set of processors into a network, while minimizing the maximum distance between these processors. Since each processor has a limited number of communication channels, a carefully planned l ..."
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Cited by 5 (1 self)
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The Processor Configuration Problem (PCP) is a Constraint Optimization Problem. The task is to link up a finite set of processors into a network, while minimizing the maximum distance between these processors. Since each processor has a limited number of communication channels, a carefully planned
Evaluation of different multithreaded and multicore processor configurations for soPC
- Embedded Computer Systems: Architectures, Modeling, and Simulation, 9th International Workshop, SAMOS, volume 5657 of Lecture Notes in Computer Science
, 2009
"... Abstract. Multicore processors get more and more popular, even in embedded systems. Unfortunately, these types of processors require a special kind of programming technique to offer their full performance, i.e. they require a high thread-level parallelism. In this paper we evaluate the performance ..."
Abstract
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Cited by 3 (1 self)
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of different configurations of the same processor core within an SoPC: a single threaded single core, a multithreaded single core, a single threaded multicore, and a multithreaded multicore. The used core is the jamuth core, a multithreaded Java processor able to execute Java bytecode directly in hardware
Optimizing Performance of Parallel Architectures Through Processor Configuration and Data Distribution
, 1999
"... Efficient performance of highly parallel systems is a crucial problem. This paper presents a method for optimizing performance through effective logical configuration of processors and distribution of data. The paper extends a parallel system performance model for total execution time and a method t ..."
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Efficient performance of highly parallel systems is a crucial problem. This paper presents a method for optimizing performance through effective logical configuration of processors and distribution of data. The paper extends a parallel system performance model for total execution time and a method
Simultaneous Multithreading: Maximizing On-Chip Parallelism
, 1995
"... This paper examines simultaneous multithreading, a technique permitting several independent threads to issue instructions to a superscalar’s multiple functional units in a single cycle. We present several models of simultaneous multithreading and compare them with alternative organizations: a wide s ..."
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Cited by 823 (48 self)
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superscalar, a fine-grain multithreaded processor, and single-chip, multiple-issue multiprocessing architectures. Our results show that both (single-threaded) superscalar and fine-grain multithreaded architectures are limited in their ability to utilize the resources of a wide-issue processor. Simultaneous
ªParallel Processor Configuration Design with Processor/Transmission Costs,º State Univ. of New York at Stony Brook
- College of Eng. and Applied Science
"... AbstractÐA computer configuration design problem where the objective is to configure a parallel processor to do processing in a cost effective manner is examined. The application envisioned is a specialized on-line service that rents time on its machine. The combinatorial optimization problem involv ..."
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Cited by 7 (4 self)
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AbstractÐA computer configuration design problem where the objective is to configure a parallel processor to do processing in a cost effective manner is examined. The application envisioned is a specialized on-line service that rents time on its machine. The combinatorial optimization problem
Clustered Speculative Multithreaded Processors
, 1999
"... In this paper we present a processor microarchitecture that can simultaneously execute multiple threads and has a clustered design for scalability purposes. A main feature of the proposed microarchitecture is its capability to spawn speculative threads from a single-thread application at run-time. T ..."
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Cited by 180 (10 self)
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In this paper we present a processor microarchitecture that can simultaneously execute multiple threads and has a clustered design for scalability purposes. A main feature of the proposed microarchitecture is its capability to spawn speculative threads from a single-thread application at run
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