### Table 8. Maximum stresses and their corresponding locations Stresses

### Table 1. Stress results.

1997

"... In PAGE 12: ... This section highlights some of the significant results from the finite-element analysis. Stress Results Table1 shows a summary of the stress results and factors of safety of the most critical components for four of the analysis cases studied. As these results show, all critical glove components are well below the allowable stress with an acceptable margin of safety.... ..."

### Table 5-3 Stress Vectors and the Stressed Transistors for a Fully Complementary CMOS Logic Gate

"... In PAGE 60: ...shortens significantly when Eox is higher than 6 MV/cm. Table5 -2 lists Eox at normal operating voltages for several technologies. For these technologies, Eox at the normal operating voltage is well below 6MV/cm.... In PAGE 60: ... For these technologies, Eox at the normal operating voltage is well below 6MV/cm. In Table5 -2, Vdd is the supply voltage and Xox is the oxide thickness. Similar to burn-in, SHOVE can shorten the lifetime of the defective devices and that of a flawless device.... In PAGE 60: ... After SHOVE, although the lifetime of the flawless device is shortened, it is still reasonably long. Table5 -1 shows that the lifetime of the flawless oxide is 20,041 years after being stressed at 6V (Eox = 6.... In PAGE 60: ...o 0.13 seconds at the recommended stress voltage. I Eox 6MV/cm Figure 5-3 Fowler-Nordheim Tunneling Current vs. Eox Table5 -1 Lifetime of a Flawless Oxide for a 3.3V Technology Vox Eox(MV/cm) tBD 3.... In PAGE 61: ... Table5 -2 Maximum Eox at Normal Operating Voltages Technologies Vdd (V) Xox(nm) Eox(MV/cm) [Schutz 94] 5 15 3.33 [Charnas 95] 3.... In PAGE 63: ...ocated. 100% toggle test sets may miss some transistors. Figure 5-4 shows a fully complementary CMOS gate. Table5 -3 shows how transistors are stressed by stress vectors. The four italicized rows include a set of 100% stuck-at test set.... In PAGE 63: ... A B C A B C OUT MPA MPB MPC MNA MNB MNC Figure 5-5 A Fully Complementary CMOS Logic Gate Because not all transistors are stressed by each test vector, some transistors may be stressed longer than others after a test set is applied. Table5... In PAGE 64: ... Because not all transistors are stressed by each test vector, some transistors may be stressed longer than others after a test set is applied. Table5 -3 shows that all-zero vectors can stress all PMOS transistors and all-one vectors can stress all NMOS transistors at once. To stress all transistors evenly and reduce the stress time for fully complementary CMOS logic gates, all-one and all-zero vectors can perform better than stuck-at test sets and pseudo stuck-at test sets as the stress vectors.... In PAGE 64: ...Because not all transistors are stressed by each test vector, some transistors may be stressed longer than others after a test set is applied. Table5 -3 shows that all-zero vectors can stress all PMOS transistors and all-one vectors can stress all NMOS transistors at once. To stress all transistors evenly and reduce the stress time for fully complementary CMOS logic gates, all-one and all-zero vectors can perform better than stuck-at test sets and pseudo stuck-at test sets as the stress vectors.... In PAGE 66: ...block consisting of domino logic in the stress condition. Table5 -4 summarizes the discussion of the stress vectors for CMOS domino logic. Table 5-4 Stress Vectors for the CMOS Domino Circuit of Fig.... In PAGE 66: ... Table 5-4 summarizes the discussion of the stress vectors for CMOS domino logic. Table5 -4 Stress Vectors for the CMOS Domino Circuit of Fig. 5-5 Input Condition MCH MEV MP MN MA MB MC Precharge Phase X* X Evaluation Phase with All-one at the Inputs X X XXX * the transistor is stressed during the described input condition 5.... ..."

### Table 3 Stress vectors and the stressed transistors for a fully complementary CMOS logic gate A B C MPA MPB MPC MNA MNB MNC

1997

"... In PAGE 11: ... Figure 4 shows a fully complementary CMOS gate. Table3 shows how transistors are stressed by stress vectors. The four italicized rows include a set of 100% stuck-at test set.... In PAGE 11: ... Because not all transistors are stressed by each test vector, some transistors may be stressed longer than others. Table3 shows that all-zero vectors can stress all PMOS transistors and all-one vectors can stress all NMOS transistors at once. To stress all transistors evenly and reduce the stress time for fully complementary CMOS logic gates, all-one and all-zero vectors can perform better than stuck-at test sets as the stress vectors.... ..."

Cited by 3

### Table 3 Stress vectors and the stressed transistors for a fully complementary CMOS logic gate A B C MPA MPB MPC MNA MNB MNC

"... In PAGE 4: ... Because not all transistors are stressed by each test vector, some transistors may be stressed longer than others. Table3 shows that all-zero vectors can stress all PMOS transistors and all-one vectors can stress all NMOS transistors at once. To stress all transistors evenly and reduce the stress time for fully complementary CMOS logic gates, all-one and all-zero vectors can perform better than stuck-at test sets as the stress vectors.... ..."

### TABLE II COMPARISON OF STRESSES

1998

Cited by 1

### Table 5-4 Stress Vectors for the CMOS Domino Circuit of Fig. 5-5

"... In PAGE 60: ...shortens significantly when Eox is higher than 6 MV/cm. Table5 -2 lists Eox at normal operating voltages for several technologies. For these technologies, Eox at the normal operating voltage is well below 6MV/cm.... In PAGE 60: ... For these technologies, Eox at the normal operating voltage is well below 6MV/cm. In Table5 -2, Vdd is the supply voltage and Xox is the oxide thickness. Similar to burn-in, SHOVE can shorten the lifetime of the defective devices and that of a flawless device.... In PAGE 60: ... After SHOVE, although the lifetime of the flawless device is shortened, it is still reasonably long. Table5 -1 shows that the lifetime of the flawless oxide is 20,041 years after being stressed at 6V (Eox = 6.... In PAGE 60: ...o 0.13 seconds at the recommended stress voltage. I Eox 6MV/cm Figure 5-3 Fowler-Nordheim Tunneling Current vs. Eox Table5 -1 Lifetime of a Flawless Oxide for a 3.3V Technology Vox Eox(MV/cm) tBD 3.... In PAGE 61: ... Table5 -2 Maximum Eox at Normal Operating Voltages Technologies Vdd (V) Xox(nm) Eox(MV/cm) [Schutz 94] 5 15 3.33 [Charnas 95] 3.... In PAGE 63: ...ocated. 100% toggle test sets may miss some transistors. Figure 5-4 shows a fully complementary CMOS gate. Table5 -3 shows how transistors are stressed by stress vectors. The four italicized rows include a set of 100% stuck-at test set.... In PAGE 63: ... A B C A B C OUT MPA MPB MPC MNA MNB MNC Figure 5-5 A Fully Complementary CMOS Logic Gate Because not all transistors are stressed by each test vector, some transistors may be stressed longer than others after a test set is applied. Table5... In PAGE 64: ... Because not all transistors are stressed by each test vector, some transistors may be stressed longer than others after a test set is applied. Table5 -3 shows that all-zero vectors can stress all PMOS transistors and all-one vectors can stress all NMOS transistors at once. To stress all transistors evenly and reduce the stress time for fully complementary CMOS logic gates, all-one and all-zero vectors can perform better than stuck-at test sets and pseudo stuck-at test sets as the stress vectors.... In PAGE 64: ... To stress all transistors evenly and reduce the stress time for fully complementary CMOS logic gates, all-one and all-zero vectors can perform better than stuck-at test sets and pseudo stuck-at test sets as the stress vectors. Table5 -3 Stress Vectors and the Stressed Transistors for a Fully Complementary CMOS Logic Gate A B C MPA MPB MPC MNA MNB MNC 000 X* XX 001 X X 010 X X 011 X X X 100 X X 101 X X 110 X X 111 X X X * the transistor is stressed when the vector is applied Because not all transistors are stressed by each test vector, some transistors may be stressed longer than others after a test set is applied. Table 5-3 shows that all-zero vectors can stress all PMOS transistors and all-one vectors can stress all NMOS transistors at once.... In PAGE 64: ... Table 5-3 Stress Vectors and the Stressed Transistors for a Fully Complementary CMOS Logic Gate A B C MPA MPB MPC MNA MNB MNC 000 X* XX 001 X X 010 X X 011 X X X 100 X X 101 X X 110 X X 111 X X X * the transistor is stressed when the vector is applied Because not all transistors are stressed by each test vector, some transistors may be stressed longer than others after a test set is applied. Table5 -3 shows that all-zero vectors can stress all PMOS transistors and all-one vectors can stress all NMOS transistors at once. To stress all transistors evenly and reduce the stress time for fully complementary CMOS logic gates, all-one and all-zero vectors can perform better than stuck-at test sets and pseudo stuck-at test sets as the stress vectors.... In PAGE 66: ...block consisting of domino logic in the stress condition. Table5 -4 summarizes the discussion of the stress vectors for CMOS domino logic. Table 5-4 Stress Vectors for the CMOS Domino Circuit of Fig.... ..."

### Table 2. Cyclic Stress Content of SST Test Sequence. (Stresses normalized by supersonic cruise mean stress.)

1999

"... In PAGE 7: ... The final sequence contained 105,445 stress cycles. The cyclic content of the test sequence is tabulated in Table2 . A portion of the SST spectrum sequence covering five flights is shown in Figure 4.... ..."

### Table 6 Warp test measurements (Low temperature)

"... In PAGE 12: ... 14 Table6 shows the third type of warp test, in which the material is cooled down rather than heated. As mentioned above, heating up the panel effectively post-cures it and affects the warp measurement.... ..."