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On-line Testing for FPGA
"... This paper focuses on the on-line error detection in circuits implemented in FPGAs. We have used error detection codes to ensure the self-checking property. A fault in a given combinational circuit has to be detected and signalized at the time of its appearance and before the further distribution of ..."
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This paper focuses on the on-line error detection in circuits implemented in FPGAs. We have used error detection codes to ensure the self-checking property. A fault in a given combinational circuit has to be detected and signalized at the time of its appearance and before the further distribution
Using On-line Testing for
"... Copyright and moral rights for the publications made accessible in the public portal are retained by the authors and/or other copyright owners and it is a condition of accessing publications that users recognise and abide by the legal requirements associated with these rights. • Users may download a ..."
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and print one copy of any publication from the public portal for the purpose of private study or research. • You may not further distribute the material or use it for any profit-making activity or commercial gain • You may freely distribute the URL identifying the publication in the ResearchOnline
An assessment of On-line Testing in Computer Science I
"... How do on-line tests compare with written tests in Computer Science I? Do students who do well in written tests also do well in an online test? Is an online test better or worse than a written test at assessing the problem-solving abilities of the student? This paper summarizes the answers to these ..."
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How do on-line tests compare with written tests in Computer Science I? Do students who do well in written tests also do well in an online test? Is an online test better or worse than a written test at assessing the problem-solving abilities of the student? This paper summarizes the answers
Low-Cost On-Line Test for Digital Filters
- IN VTS
, 1999
"... A low-cost on-line test scheme for digital filters is proposed. The scheme uses an invariant of the digital filter, the frequency response at specific points, in order to detect possible malfunctioning of the circuit. The analysis performed indicates that 100% fault secureness is possible, if certai ..."
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Cited by 3 (0 self)
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A low-cost on-line test scheme for digital filters is proposed. The scheme uses an invariant of the digital filter, the frequency response at specific points, in order to detect possible malfunctioning of the circuit. The analysis performed indicates that 100% fault secureness is possible
ON-LINE TESTING AND DIAGNOSIS OF MICROCONTROLLERS
"... During its lifetime, a digital system is tested and diagnosed on numerous occasions. For the system to perform its intended mission with high availability, testing and diagnosis must be quick and effective. A sensible way to ensure this is to specify testing as one of the system functions – in other ..."
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During its lifetime, a digital system is tested and diagnosed on numerous occasions. For the system to perform its intended mission with high availability, testing and diagnosis must be quick and effective. A sensible way to ensure this is to specify testing as one of the system functions
An On-Line Testing Approach Using Code-Perturbation
"... is tested. However. this is too expensive and impractical. In practice on-line testing is conducted using codes that are of-This paper presents an efficient on-line testing approach ten too abstract. though may be easy to execute. The objec-that uses application programs as the test inputs. The apti ..."
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is tested. However. this is too expensive and impractical. In practice on-line testing is conducted using codes that are of-This paper presents an efficient on-line testing approach ten too abstract. though may be easy to execute. The objec-that uses application programs as the test inputs
Efficient On-line Testing of FPGAs with Provable Diagnosabilities
- Proc. Design Automation Conf. (DAC
, 2004
"... We present novel and efficient methods for on-line testing in FPGAs. The testing approach uses a ROving TEster (ROTE), which has provable diagnosabilities and is also faster than prior FPGA testing methods. We present 1- and 2-diagnosable built-in self-tester (BISTer) designs that make up the ROTE, ..."
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Cited by 5 (1 self)
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We present novel and efficient methods for on-line testing in FPGAs. The testing approach uses a ROving TEster (ROTE), which has provable diagnosabilities and is also faster than prior FPGA testing methods. We present 1- and 2-diagnosable built-in self-tester (BISTer) designs that make up the ROTE
Using Concurrent and Semi-concurrent On-line Testing During HLS:
"... This paper proposes a suitable on-line testing technique during the synthesis of complex electronic structures. Online testability is addressed by exploiting time redundancy in the scheduled data flow graph. On-line testability constraints are taken into account at the scheduling and allocation task ..."
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This paper proposes a suitable on-line testing technique during the synthesis of complex electronic structures. Online testability is addressed by exploiting time redundancy in the scheduled data flow graph. On-line testability constraints are taken into account at the scheduling and allocation
Development of On-Line Test Materials with a Checklist for Information Literacy Education
"... Abstract: We report on the development of on-line test (exam) materials for information literacy education with the use of a checklist. Some points of view to improve materials have been known by prior studies and we could collect and list up checking items to assess and improve on-line test materia ..."
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Abstract: We report on the development of on-line test (exam) materials for information literacy education with the use of a checklist. Some points of view to improve materials have been known by prior studies and we could collect and list up checking items to assess and improve on-line test
On-line Testing of Routers in Networks-on-Chips
"... Due to recent progress in semiconductor technology, communication is becoming the major source of expense in today’s chip design. Network-on-Chip (NoC) is a new paradigm for solving the problem of complex communication on the chips. However, in order to NoC to be efficient in providing complex on-ch ..."
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online test). Moreover it should test the NoC with a high fault coverage (structural test). In this thesis, a new platform is proposed to do online-structural test on NoC. Although NoC’s elements has been tested after manufacturing and before being used in a SoC,
Results 1 - 10
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3,820